IRF7401 datasheet(15/24 Pages) AD

15 / 24 page

REV. C

ADN8830

–15–

OUT B

PVDD

OUT A

DENOTES

PGND

Figure 14. Equivalent Circuit for PWM Amplifier and Filter

In this circuit, RL is the TEC resistance, R2 is the parasitic

resistance of the inductor combined with the equivalent rDS, ON

of Q1 and Q2, and R1 is the ESR of C1. The voltage, VX, is the

pulse-width modulated waveform that switches between PVDD

and ground. This is a second-order low-pass filter with an exact

cutoff frequency of

C L

()

11 1

(25)

Practically speaking, R1 and R2 are several tens of milliohms and

are much smaller than the TEC resistance, which can be a few

ohms. The cutoff frequency can be roughly approximated as

(26)

This cutoff frequency should be much lower than the clock

frequency to achieve adequate filtering of the switched output

waveform. Also of importance is the damping factor, , of the

L-C filter. Too low a damping factor will result in a longer

settling time and could potentially cause stability problems for

the temperature control loop. Neglecting R1 and R2 again, the

damping factor is simply

ζ =

(27)

Using the recommended values of L1 = 4.7

µH and C1 = 22 µF

results in a cutoff frequency of 15.7 kHz. With a TEC resistance

of 2

Ω, the damping factor is 0.12. The cutoff frequency can be

decreased to lower the output voltage ripple with slower clock

frequencies by increasing L1 or C1. Increasing C1 may appear

to be a simpler approach as it would not increase the physical

size of the inductor, but there is a potential stability danger in

lowering the damping factor too far. It is recommended that

remain greater than 0.05 to provide a reasonable settling time

for the TEC. Increasing

ζ also makes finding the proper PID

compensation easier as there is less ringing in the L-C output

filter. To allow adequate phase and gain margin for the PWM

amplifier, Table III should be used to find the lower limit of

cutoff frequency for a given damping factor.

Table III. Minimum L-C Filter Cutoff

Frequency vs. Damping Factor

fC, MIN (kHz)

0.05

0.1

0.2

0.3

1.9

0.5

1.6

> 0.707

1.5

Calculating PWM Output Ripple Voltage

Although it may seem that fC can be arbitrarily lowered to reduce

output ripple, the ripple voltage is also dependent on the ESR of

C1, shown as R1 in Figure 14. This resistance creates a zero

that turns the second-order filter into a first-order filter at high

frequencies. The location of this zero is

21 1

(28)

With a clock frequency greater than Z1, and presumably greater

than fC, the output voltage ripple is

∆∆

OUT A

=× 1

(29)

∆OUT A

D R

for f

CLK

()

–

(30)

The worst-case voltage ripple occurs when the duty cycle of the

PWM output is exactly 50%, or when OUT A = 0.5

VDD. As

shown in Equation 31

OUT A

for f

MAX

CLK

≈>

()

(31)

Here it can be directly seen that increasing the inductor value or

clock frequency will reduce the ripple. Choosing a low ESR

capacitor will ensure R1 remains low. Operating from a lower

supply voltage will also help reduce the output ripple voltage

from the L-C filter. With a clock frequency equal to Z1 but

presumably greater than fC, the worst-case output voltage ripple is

∆OUT A

LC f

for f

MAX

CLK

()

16 1

32 1 1

(32)

Which, if fCLK < Z1, can be further simplified to

∆OUT A

LC f

for f

MAX

CLK

()

32 1 1

(33)

A typical 100

µF surface-mount electrolytic capacitor can have

an ESR of over 100 m

Ω, pulling this zero to below 16 kHz, and

resulting in an excess of ripple voltage across the TEC. Low ESR

capacitors, such as ceramic or polymer aluminum capacitors,

are recommended instead. Polymer aluminum capacitors can

provide more bulk capacitance per unit area over ceramic ones,

saving board space. Table IV shows a limited list of capacitors

with their equivalent series resistances.

This is by no means a complete list of all capacitor manufacturers

or capacitor types that can be used in the application. The 22

µF

capacitor recommended has a maximum ESR of 35 m

Ω, which

puts Z1 at 207 kHz. Using a 3.3 V supply with the recommended

inductor and capacitor listed with a 1 MHz clock frequency will

yield a worst-case ripple voltage at OUT A of about 6 mV.

External FET Requirements

External FETs are required for both the PWM and linear amplifiers

that drive OUT A and OUT B from the ADN8830. Although it

is important to select FETs that can supply the maximum current

required to the TEC, they should also have a low enough resis-

tance (rDS, ON) to prevent excessive power dissipation and improve

efficiency. Other key requirements from these FET pairs are

slightly different for the PWM and linear outputs.

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