CAT25M02

www.onsemi.com

9

Write Status Register

The Status Register is written by sending a WRSR

instruction according to timing shown in Figure 7. Only bits

2, 3, 4, 5, 6 and 7 can be written using the WRSR command.

Write Protection

The Write Protect (WP) pin can be used to protect the

Block Protect bits BP0 and BP1 against being inadvertently

altered. When WP is low and the WPEN bit is set to “1”,

write operations to the Status Register are inhibited. WP

going low while CS is still low will interrupt a write to the

status register. If the internal write cycle has already been

initiated, WP going low will have no effect on any write

operation to the Status Register. The WP pin function is

blocked when the WPEN bit is set to “0”. The WP input

timing is shown in Figure 8.

Figure 7. WRSR Timing

01

2

3

4

5

6

7

8

10

911

12

13

14

SCK

SI

MSB

HIGH IMPEDANCE

DATA IN

15

SO

7

6

5

4

3

2

10

00

0

00

0

0

1

OPCODE

Note: Dashed Line = mode (1, 1)

CS

Figure 8. WP Timing

SCK

WP

Note: Dashed Line = mode (1, 1)

CS

WP