LM2645 datasheet(15/20 Pages) NSC

15 / 20 page

Operation Descriptions

General

The LM2645 integrates two synchronous switching control-

lers, one adjustable linear regulator controller and one fixed

3.3V output into a single package. It solves the need within

many portable systems for 5V, 3.3V, 3.3V stand-by and 12V

legacy power supplies.

The two switching controllers, Channel 1 and Channel 2,

operate 180˚ out of phase to reduce input capacitor size and

cost. They can be independently enabled and disabled. The

external linear regulator controller, or Channel 4, can also be

independently enabled and disabled when Channel 1 has

been enabled.

The output voltages of channel 1 and channel 2 can be set

between 1.3V to 5.5V by external voltage divider, or fixed at

5V and 3.3V respectively without the need of external volt-

age divider. The output voltage of Channel 4 is adjustable

from 3.3V to 15V.

Both switching channels use synchronous rectification and

employ a peak current mode control scheme. Protection

features include over-voltage protection (Ch1 and 2),

under-voltage protection (Ch1, 2 and 4), and positive and

negative peak current limit (Ch1 and 2). UVP function can be

disabled or delayed by an arbitrary amount of time. The

device operates with a wide input voltage range from 5.5V to

30V. The outputs of the two switching channels have inde-

pendent power good monitoring. Channel 1 and channel 2

can be configured to operate in parallel as a dual phase

switching converter for high power applications

Soft Start

In normal operation the soft-start functions as follows. As the

input voltage rises above the 4.2V UVLO threshold, the

internal circuitry is powered on, an internal 2µA current starts

to charge the capacitor connected between the SSx pin and

ground, and the corresponding channel is turned on. A MI-

N_ON_TIME comparator generates the soft start PWM

pulses. As the SSx pin voltage ramps up, the duty cycle

increases, causing the output voltage to ramp up. During this

time, the error amplifier output voltage is clamped at 0.8V,

and the duty cycle generated by the PWM comparator is

ignored. When the corresponding output voltage exceeds

98.5% (typical) of the set target voltage, the regulator tran-

sitions from soft-start to operating mode. Beyond this point,

once the PWM pulses generated by the PWM comparator

are wider than those generated by the MIN_ON_TIME com-

parator, the PWM comparator takes over and starts to regu-

late the output voltage. At the same time, the high clamp at

the output of the error amplifier is switched to 2V. That is,

peak current mode control now takes place.

The rate at which the duty cycle increases depends on the

capacitance of the soft start capacitor. The higher the ca-

pacitance, the slower the output voltage ramps. A unique

feature of the LM2645 is that the rate at which the duty cycle

grows is independent of the input voltage. This is because

the ramp signal used to generate the soft start duty cycle has

a peak value proportional to the input voltage, making the

product of duty cycle and input voltage a constant. This

makes the soft start process more predictable and reliable.

During soft start, under-voltage protection is temporarily sus-

pended, but over-voltage protection and current limit remain

in effect. When the SSx pin voltage exceeds 2V, a soft start

time out signal (sstox) will be issued. This signal sets the

under-voltage

protection

into

ready

mode.

See

the

Under-Voltage Protection section.

If either the SS1 or SS2 pin is short-circuited to ground

before startup, the corresponding channel will operate at

minimum

duty

cycle

when

enabled,

and

the

under-voltage protection of that channel will be disabled.

However, if the soft start has been completed and the output

voltage has been established, then short-circuiting the SSx

pin to ground does not affect the normal operation and

under-voltage protection of that channel.

Shut Down Latch State

This state is typically caused by an output under-voltage or

over-voltage event. In this state, both switching channels

have their top FETs turned off and their bottom FETs turned

on (See the Ch1 and 2 output capacitors discharge section).

The LDODRV pin will be shut down, but VLIN5 and OUT3

will remain unaffected.

There are two methods to release the system from the latch

off state. One is to cycle the input voltage. Another method is

to pull the SD pin below 0.6V and release it HIGH again.

After the latch is released, the two switching channels will go

through the normal soft start process.

Ch 1 and 2 Output Capacitors Discharge

Each switching channel has an embedded 200

Ω MOSFET

with the drain connected to the VOx pin. This MOSFET will

discharge the output capacitor of that channel if that channel

is turned off due to one of the following events:

Its ONx pin is pulled low to below 0.8V.

The IC enters shut down mode or fault state.

The IC enters shut down latch state caused by an output

under-voltage event.

When the output capacitor has been discharged to about

0.8V, the bottom gate-drive (LDRVx) will be turned on, driv-

ing on the bottom FET to discharge the output capacitor

through the filter inductor.

If an output over-voltage event occurs, the HDRVx will be

turned off and the LDRVx will be turned on immediately

regardless of the level of output voltage, thus discharging the

output capacitor through the filter inductor.

When that channel is released from the shutdown latch state

or returned to the on state, it will go through the soft start

process to recover the output voltage.

Fault State

If the input voltage drops to less than 3.9V, or the IC enters

thermal shut down mode, a

″fault″ signal will be generated

internally. This signal will discharge the capacitor connected

between the SSx pin and ground with 24µA of current until

the SSx pin reaches 50mV. This will turn off both switching

channels.

Force PWM Mode

This mode applies to both switching channels simulta-

neously. The force-PWM mode is activated by pulling the

FPWM/2NDFB pin to logic low. In this mode, the top FET

and the bottom FET gate signals are always complementary

to each other and the NEGATIVE CURRENT LIMIT com-

parator is activated (see

Negative Current Limit section). In

force-PWM mode, the regulator always operates in Continu-

ous Conduction Mode (CCM) and its duty cycle (approxi-

mately Vout / Vin) is almost independent of load.

LM2645 Datasheet(PDF) 15 Page - National Semiconductor (TI)

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