LM26 datasheet(14/20 Pages) NSC

14 / 20 page

Operation Descriptions (Continued)

typical) both channels will latch off. Also, UV_DELAY will be

disabled and the UV_DELAY pin will return to 0V. During

UVP, both the high side and low side FET drivers will be

turned off. If no capacitor is connected to the UV_DELAY pin,

the UVP latch will be activated immediately. To reset the

UVP latch, either the input voltage must be cycled, or both

ON/SS pins must be pulled low. The UVP function can be

disabled by connecting the UV_DELAY pin to ground.

POWER GOOD

A power good pin (PGOOD1) is available to monitor the

output status of Channel 1. As shown in Figure 5, the pin

connects to the output of an open drain MOSFET, which will

remain open while Channel 1 is within operating range.

PGOOD1 will go low (low impedance to ground) under the

following four conditions:

Channel 1 is turned off

Channel 1 output falls below 90.3% of nominal (UVPG1)

OVP on either channel

UVP on either channel

When on, the PGOOD1 pin is capable of sinking 0.95mA

(typical). If an OVP or UVP condition occurs, both channels

will latch off, and the PGOOD1 pin will be latched low. During

a UVPG1 condition, however, PGOOD1 will not latch off. The

pin will stay low until Channel 1 output voltage returns to

94% (typical) of nominal. See Vpwrgd in the Electrical Char-

acteristics table.

OUTPUT CAPACITOR DISCHARGE

Each channel has an embedded 480

Ω MOSFET with the

drain connected to the SWx pin. This MOSFET will dis-

charge the output capacitor of its channel if its channel is off,

or the IC enters a fault state caused by one of the following

conditions:

UVP

UVLO

Thermal shut-down (TSD)

If an output over voltage event occurs, the HDRVx will be

turned off and LDRVx will be turned on immediately to

discharge the output capacitor of both channels through the

inductor.

SWITCHING NOISE REDUCTION

Power MOSFETs are very fast switching devices. In syn-

chronous rectifier converters, the rapid increase of drain

current in the top FET coupled with parasitic inductance will

generate unwanted Ldi/dt noise spikes at the source node of

the FET (SWx node) and also at the VIN node. The magni-

tude of this noise will increase as the output current in-

creases. This parasitic spike noise may turn into electromag-

netic interference (EMI), and can also cause problems in

device performance. Therefore, it must be suppressed using

one of the following methods.

It is strongly recommended to add R-C filters to the current

sense amplifier inputs as shown in Figure 7. This will reduce

the susceptibility to switching noise, especially during heavy

load transients and short on time conditions. The filter com-

ponents should be connected as close as possible to the IC.

As shown in Figure 6, adding a resistor in series with the

SWx pin will slow down the gate drive (HDRVx), thus slowing

the rise and fall time of the top FET, yielding a longer drain

current transition time.

Usually a 3.3

Ω to 4.7Ω resistor is sufficient to suppress the

noise. Top FET switching losses will increase with higher

resistance values.

Small resistors (1-5 ohms) can also be placed in series with

the HDRVx pin or the CBOOTx pin to effectively reduce

switch node ringing. A CBOOT resistor will slow the rise time

of the FET, whereas a resistor at HDRV will reduce both rise

and fall times.

CURRENT SENSING AND LIMITING

As shown in Figure 7, the KSx and RSNSx pins are the

inputs of the current sense amplifier. Current sensing is

accomplished either by sensing the Vds of the top FET or by

sensing the voltage across a current sense resistor con-

nected from VIN to the drain of the top FET. The advantage

of sensing current across the top FET are reduced parts

count, cost and power loss, whereas using a current sense

resistor improves the current sense accuracy. Keeping the

differential current-sense voltage below 200mV ensures lin-

ear operation of the current sense amplifier. Therefore, the

Rdson of the top FET or the current sense resistor must be

small enough so that the current sense voltage does not

exceed 200mV when the top FET is on. There is a leading

edge blanking circuit that forces the top FET on for at least

166ns. Beyond this minimum on time, the output of the PWM

comparator is used to turn off the top FET. Additionally, a

minimum voltage of at least 50mV across Rsns is recom-

mended to ensure a high SNR at the current sense amplifier.

Assuming a maximum of 200mV across Rsns, the current

sense resistor can be calculated as follows:

where Imax is the maximum expected load current, including

overload multiplier (ie:120%), and Irip is the inductor ripple

current (See equation 7). The above equation gives the

maximum allowable value for Rsns. Switching losses will

increase with Rsns, thus lowering efficiency.

The peak current limit is set by an external resistor con-

nected between the ILIMx pin and the KSx pin. An internal

10µA current sink on the ILIMx pin produces a voltage

across the resistor to set the current limit threshold which is

compared to the current sense voltage. A 10nF capacitor

across this resistor is required to filter unwanted noise that

could improperly trip the current limit comparator.

20046209

FIGURE 6. SW Series Resistor

LM26 Datasheet(PDF) 14 Page - National Semiconductor (TI)

LM26 Datasheet(HTML) 14 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL