TAS5001

SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

15

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PARAMETER MEASUREMENT INFORMATION

16-Bit Left Channel Data

16-Bit Left Channel Data

32-Bit Ignore

tw(FSHIGH)

64 SCLKs

16-Bit Left Channel Data

SCLK

LRCLK

SDIN

Figure 15. DSP Serial Port Expanded Timing

tsu(SDIN) = 20 ns

th(SDIN) = 10 ns

SCLK

SDIN

NOTE: Serial data is sampled with the falling edge of SCLK (setup time = 20 ns and hold time = 10 ns)

Figure 16. DSP Absolute Timing Requirement