IP1001 datasheet(14/18 Pages) IRF

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iP1001

The schematics in Fig.10a & 10b and complete Bill

of Materials in Table 4 are provided as a reference

design to enable a preliminary evaluation of iP1001.

They represent a simple method of applying the

iP1001 solution in a synchronous buck topology.

Fig. 10a shows the implementation for <5V

nominal applications, and Fig. 10b shows the

implementation for 5V

- 12V

nominal

applications.

The connection pins are provided through the solder

balls on the bottom layer of the package. A total

power supply solution is presented with the addition

of inductor L1 and the output capacitors C11-C14.

Input capacitors C1-C10 are for bypassing in the

IN - 12VIN application, but only C1-C3 are required

for <5V

IN applications (refer to the BOM for values).

Switches 1-5 of SW1 are used to program the output

voltage. Refer to the VID table provided in this

datasheet for the code that corresponds to the

desired output voltage. Resistors R2 & R4 need to

be removed for operation at standard VID levels

(0.925V - 2.0V, leave R3 = 0

Ω). Switch 8 of SW1

enables the output when floating (internally pulled

high). The 5V V

DD power terminal and input power

terminals are provided as separate inputs. They

can be connected together if the application

requires only 5V nominal input voltage.

The reference design also offers a higher output

voltage option for greater than 2.0V, up to 3.3V. For

output voltages above 2V, the DAC setting must be

set to 2V, and then select resistors R3 & R4 per

Equation 1 on page 10 for the desired output volt-

age. Remove R5 and connect V

F to VFS through R2,

where R2=0

Ω. In this case, GNDS should be refer-

enced to PGND. Tighter regulation can be achieved

by using resistors with less than 1% tolerance. For

Vin < 5V and Vout > 2V, the frequency select pin

(FREQ) must be set to 200kHz (connected to V

DD).

For applications with V

IN < 5V and where there is no

auxiliary 5V available, connections JP2 and JP3

must be provided in order to enable the boost cir-

cuit. This will provide 5V V

DD necessary for the

iP1001 internal logic to function. The boost circuit

will convert 3.3V input voltage to 5V, to power the

DD, and will provide enough power to supply the

internal logic for up to five iP1001 power blocks.

iP1001 Reference Design

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