83C694 datasheet(13/33 Pages) ETC

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NUMBER

MNEMONIC

SIGNAL NAME

I/O

DESCRIPTION

COL

Collision Detect

A 10 MHz (+25%,-15%) signal at the CD

inputs (DTE mode) produces a logic high at

the COL output. When no signal is present at

the CD inputs, the COL output goes low. In

10BaseT operation, the COL output goes high

when TPR+ and TPR- are active while a

packet is being transmitted on TPX+/TPX-.

COL also goes high during SQE test or jabber

condition.

No Connect

Do not connect any circuitry to this pin.

RXD

Receive Data

This is the NRZ data output from the on-chip

decoder and phase-locked loop. This signal

should be sampled by the controller at the

rising edge of receive clock. A high level is

binary "one", a low level is binary "zero".

CRS

Carrier Sense

CRS (DTE mode) goes high when valid data

i s presen t at the R X+/R X- i np uts or

TPR+/TPR- inputs. It goes low after the last

bit is received at the inputs.

RES

Reset/Synch

When RES is low, all internal nodes are set to

a known state except for internal clock distri-

bution.

This improves testing procedures.

Normal operation is enabled on the rising

edge of RES and while RES is high. The RES

pin includes an internal pull up resistor, so it

may be left open if unused.

RXC

Receive Clock

When the phase-locked loop acquires a valid

receive signal, a 10MHz clock signal (recov-

ered from receive data) is output on RXC.

RXC is low during idle (5 bit times after re-

ceive activity stops).

SEL

Mode Select

When SEL is high, TX+ and TX- outputs are

at the same voltage in idle state, providing a

"zero" differential. When SEL is low, TX+ is

positive with respect to TX- in idle state. Also,

three test modes may be selected by setting

the SEL pin to voltages between low and high

levels. Refer to section 2.13 for more on test

modes.

TABLE 3-1. PIN DESCRIPTION

83C694D

PIN DESCRIPTION

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