LM2698 datasheet(15/17 Pages) NSC

15 / 17 page

Application Information (Continued)

Level-Shifted SEPIC

The circuit shown in

Figure 8 is similar to the SEPIC shown

Figure 7, except that it is level shifted to provide a negative

output voltage. This is achieved by connecting the ground of

the LM2698 to the output. The circuit analysis for the

level-shifted SEPIC is the same as the SEPIC. The voltage

at the input of the LM2698 will need to be clamped if the

absolute value of the output voltage plus the input voltage

exceeds 12V, the absolute maximum rating for the V

IN pin.

The simplest way to do this is with a zener diode, as shown

Figure 8. Likewise, if the FSLCT pin is pulled high to

operate at 1.25 MHz, its voltage must not exceed 12V. To

prevent any high frequency noise from entering the

LM2698’s internal circuitry, a high frequency bypass capaci-

tor must be placed as close to pin 6 as possible. A good

choice for this capacitor is a 0.1µF ceramic capacitor.

Power Dissipation

The output power of the LM2698 is limited by its maximum

power dissipation. The maximum power dissipation is deter-

mined by the formula

D =(Tjmax -TA)/θJA

where T

jmax is the maximum specified junction temperature

(125˚C), T

A is the ambient temperature, and θJA is the ther-

mal resistance of the package.

JA is dependant on the

layout of the board as shown below.

20012611

20012612

20012643

FIGURE 8. Level-Shifted SEPIC Converter

LM2698 Datasheet(PDF) 15 Page - National Semiconductor (TI)