ADA4622-2 datasheet(22/28 Pages) AD

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ADA4622-2

Data Sheet

Rev. 0 | Page 22 of 28

THEORY OF OPERATION

SLEW

ENHANCEMENT

CIRCUIT

ED1

+INx

V–

OUTx

V+

–INx

ED2

R10

OUTPUT

STAGE

VBIAS

OUT1

OUT2

ED3

ED4

ED5

ED6

IMAGIC

CURRENT

CURRENT MIRROR

Figure 71. Simplified Circuit Diagram

INPUT CHARACTERISTICS

The ADA4622-2 input stage consists of N-channel JFETS

that provide low offset, low noise, and high impedance. The

minimum input common-mode voltage extends from 200 mV

below V− to 1 V less than V+. Driving the input closer to the

positive rail causes loss of amplifier bandwidth and increased

common-mode voltage error. Figure 72 shows the rounding of

the output due to the loss of bandwidth. The input and output

are superimposed.

CH1 1.00V CH2 1.00V

M2.00µs

A CH1

3.00V

Figure 72. Bandwidth Limiting Due to Headroom Requirements

The ADA4622-2 does not exhibit phase reversal for input

voltages up to V+. For input voltages greater than V+, a 10 kΩ

resistor in series with the noninverting input prevents phase

reversal at the expense of higher noise (see Figure 73).

CH1 1.00V CH2 1.00V

M2.00µs

A CH1

3.84V

Figure 73. No Phase Reversal

Because the input stage uses N-channel JFETs, the input current

during normal operation is negative. However, the input bias

current changes direction as the input voltage approaches V+

due to internal junctions becoming forward biased (see Figure 74).

–3

–2

–1

–5

–4

–3

–2

–1

COMMON-MODE VOLTAGE (V)

Figure 74. Input Bias Current vs. Common-Mode Voltage with ±5 V Supply

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