DocID17922 Rev 6

11/18

STM8AL3xxx STM8L052R8 STM8L1xxx6/8

Silicon limitations

17

1.2

System limitations

1.2.1

Default DAC output level when output buffer is enabled

Description

When the DAC is enabled in buffered mode configuration, the output is set to a voltage

which corresponds to the code 0xFFF, whatever the data output register value. The output

recovers the correct voltage as soon as a new data is written into the data holding register.

Workaround

None.

The following software sequence must be executed at the highest speed to limit the duration

of this transient behavior:

DAC->CR1=01; //Enable DAC

DAC->DHR8 = 0x0; //Update the data holding register with 0 (as

an example), or with any other data.

Note:

The DAC in unbuffered mode is not affected by this limitation.

1.2.2

32.768 kHz LSE crystal accuracy may be disturbed by the use of



adjacent I/Os

Description

The activity on the PC4 and PC7 I/Os (input or output) can lead to missing pulses on the low

speed external oscillator (32.768 kHz external crystal).

Workaround

None.

No fix planned for this limitation.

1.2.3

RTC LSE failure can be detected just once after power-on reset

Description

When the CSS on LSE is enabled (CSSEN=1 in CSSLSE_CSR), the CSS on LSE Flag

(CSSF) can be set only once after power-on reset. Consequently, in case of several LSE

perturbations in the application, only the first one can be detected and set the CSSF flag.

Workaround

None.

No fix planned for this limitation.