DocID17922 Rev 6

15/18

STM8AL3xxx STM8L052R8 STM8L1xxx6/8

Silicon limitations

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Workaround

If the master device supports it, use the clock stretching mechanism by programming the bit

NOSTRETCH=0 in the I2C_CR1 register.

If the master device does not support it, ensure that the write operation to the data register

is performed just after TXE or ADDR events. You can use an interrupt on the TXE or ADDR

flag and boost its priority to the higher level or use DMA.

being late to write the DR register (second condition).

Note:

The first data to be transmitted must be written into the data register after the ADDR flag is

cleared, and before the next SCL rising edge, so that the time window to write the first data

If this is not possible, a possible workaround can be the following:

1.

Clear the ADDR flag

2.

Wait for the OVR flag to be set

3.

Clear OVR and write the first data.

The time window for writing the next data is then the time to transfer one byte. In that case,

the master must discard the first received data.

SMBus standard not fully supported in I2C peripherals

Description

support the capability to NACK an invalid byte/command.

Workarounds

A higher-level mechanism should be used to verify that a write operation is being performed

correctly at the target device, such as:



The use of the SMBA pin if supported by the host



The alert response address (ARA) protocol



The Host notify protocol.

1.3.3

USART peripheral limitations

USART IDLE frame detection not supported in the case of a clock deviation

Description

An idle frame cannot be detected if the receiver clock is deviated.

If a valid idle frame of a minimum length (depending on the M and Stop bit numbers) is

followed without any delay by a start bit, the IDLE flag is not set if the receiver clock is

deviated from the RX line (only if the RX line switches before the receiver clock).

Consequently, the IDLE flag is not set even if a valid idle frame occurred.

Workaround

None.

No fix planned for this limitation.