lay capacitor. When the capacitor voltage increases 3.75V

(

∆V

again set HIGH. The delay time is calculated by:

The constant, 1.9 x 10

to device. The total delay time error budget is the sum of the

20% device tolerance and the tolerance of the external ca-

pacitor. For a 20% timing capacitor tolerance, the worst case

2.33:1. In most applications the minimum expected reset

pulse is of interest. This occurs with minimum C

mum

∆V

are fully specified in the Electrical Characteristics. Graphs

showing the relationship between delay time and both tem-

perature and C

Characteristics.

As shown in

Figure 1, the delayed reset output is pulled low

by an NPN transistor (Q2), and pulled high to V

nal 30 k

Ω resistor (R3) and PNP transistor (Q3). The reset

output will operate when V

more). At lower voltages the reset output will be in a high im-

pedance condition. Because of differences in the V

and Q3 and the values of R1 and R2, Q2 is guaranteed by

design to bias

before Q3, providing a smooth transition from

the high impedance state when V

state when V

The static reset characteristics are shown in

Figure 2. This

shows the relationship between the input voltage, the regul-

tor output and reset output. Plots are shown for various ex-

ternal pull-up resistors ranging in value from 3 k

Ω to an open

circuit. Any external pull-up resistance causes the reset out-

put to follow the regulator output until Q2 is biased ON. C

DE-

LAY

has no effect on this characteristic.

Figure 2 is useful for determing reset performance at any

particular input voltage. Dynamic performance at power-up

will closely follow the characteristics illustrated in

Figure 2,

except for the delay added by C

The dynamic reset characteristics at power-down are illus-

trated by the curve shown in

Figure 3. At time t=0 the input

voltage is instantaneously brought to 0V, leaving the output

powered by C

a 100

Ω load resistor), the reset output is held low. As V

O

drops below 0.7V, the reset rises up slightly should there be

any external pull-up resistance. With no external resistance,

the reset line stays low throughout the entire power down

cycle. If the input voltage does not fall instantaneously, the

reset signal will tend to follow the performance characteris-

tics shown in

Figure 2.

SYSTEM DESIGN CONSIDERATIONS

Many microprocessors are specified for operation at 5V

this range. Others, such as certain members of the COPS

family of microcontrollers, are specified for operation as low

as 2.4V.

Of particular concern is low voltage operation, which occurs

in battery operated systems when the battery reaches the

end of its discharge cycle. Under this condition, when the

supply voltage is outside the guaranteed operating range,

the clock may continue to run and the microprocessor will at-

tempt to execute instructions. If the supply voltage is outside

the guaranteed operating range, the instructions may not ex-

ecute properly and a hardware reset such as is supplied by

DS010759-6

FIGURE 1. Delay Reset Output

DS010759-7

FIGURE 2. Reset Output Behavior during Power-Up

DS010759-8

FIGURE 3. Reset Output Behavior during Power-Down

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