TSL215

128

× 1 INTEGRATED OPTO SENSOR

SOES005A – JUNE 1992 – REVISED AUGUST 1993

4

POST OFFICE BOX 655303

detailed description (continued)

shift register

Both 64-bit shift registers control the transfer of charge from the pixels to the output stages and provide timing

signals for the NOCG. The serial input (SI) signal provides the input to the shift register and is shifted under

direct control of CLK out to the serial output (SO) on the 64th clock cycle. This SO pulse can then be used as

the SI pulse for the next section or next device.

The output period for each section is initiated by the presence of the SI input pulse coincident with a rising edge

of CLK (see Figures 1, 2, and 3). The analog output voltage corresponds to the level of the first pixel after settling

available at each rising edge of CLK. The output period of a section ends when the active section sees the rising

edge of the 65th clock cycle, at which time the output assumes the high-impedance state. Once the output

period has been initiated by an SI pulse, CLK must be allowed to complete [ (n

× 64)+1] (where n is the number

of sections running in series) positive-going transitions in order to reset the internal logic to a known state. To

achieve minimum integration time, the SI pulse may be present on the [ (n

× 64)+2] rising clock to immediately

restart the output phase.

sample-and-hold

The sample-and-hold signal generated by the NOCG is used to hold the analog output voltage of each pixel

constant until the next pixel is clocked out. The signal is sampled while CLK is high and held constant while CLK

is low.

nonoverlapping clock generators

The NOCG circuitry provides internal control signals for the sensor, including reset and pixel-charge sensing.

The signals are synchronous and are controlled by the outputs of the shift register.

initialization

Initialization of the sensor elements may be necessary on power up or during operation after any period of CLK

or SI inactivity exceeding the integration time. The initialization phase consists of 12 to 15 consecutively

performed output cycles and clears the pixels of any charge that may have accumulated during the inactive

period.

multiple-unit operation

Multiple-sensor devices can be connected together in a serial or parallel configuration. The serial connection

is accomplished by connecting analog outputs (AO) together and connecting the SO output of each sensor

device to the SI input of the next device. The SI signal is applied to only the first device. Each succeeding device

receives its SI input from the SO output of the preceding device. For m-cascaded devices, the SI pulse is applied

to the first device after every m

•128th positive-going CLK transitions. A common clock signal is applied to all

the devices simultaneously. Parallel operation of multiple devices is accomplished by supplying CLK and SI

signals to all the devices simultaneously. The output of each device is then separately used for processing.

output enable

The internally generated output-enable signal enables the output stage of each section during the output period

(64 clock cycles). During the remainder of the integration period, the output stage is in the high-impedance state

that allows output interconnections of multiple devices without interference.