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MLX80031 Datasheet(PDF) 13 Page - Melexis Microelectronic Systems |
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MLX80031 Datasheet(HTML) 13 Page - Melexis Microelectronic Systems |
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13 / 50 page ![]() MLX80050/51/30/31 LIN System Basis ICs Datasheet MLX80050/51/30/31 – Datasheet Page 13 3901080050 Jun 2016 011 19.04 slew rate rising edge LIN dV/dTrise Normal Mode LIN-Load: 1kΩ/1nF 1.0 1.5 2.5 V/ s C 19.05 slew rate falling edge LIN dV/dTfall -2.5 -1.5 -1.0 V/ s C 19.06 slew rate rising edge LIN dV/dTrise Low Slew Mode LIN-Load: 1kΩ/1nF 0.3 0.8 1.3 V/ s C 19.07 slew rate falling edge LIN dV/dTfall -1.3 -0.8 -0.3 V/ s C Internal capacity CLIN Pulse at LIN via 10kOhm with 0/10V; VS = open 25 35 pF D LIN transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 (20kbit/s) Conditions: Normal slew mode; VS =7.0V to 18V; LIN loads: 1k /1nF; 660/6.8nF; 500/10nF TxD signal: tBit = 50µs, twH = TwL = tBit; trise = tfall < 100ns Minimal recessive bit time trec(min) 40 50 58 s Maximum recessive bit time trec(max) 40 50 58 s 20.01 Duty cycle 1 D1 D1 = trec(min) / (2*tBit) 0.396 A 20.02 Duty cycle 2 D2 D2 = trec(max) / (2*tBit) 0.581 A Transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 (10.4kbit/s) Conditions: Low slew mode; VS =7.0V to 18V; LIN loads: 1k /1nF; 660/6.8nF; 500/10nF TxD signal: tBit = 96µs, twH = TwL = tBit; trise = tfall < 100ns Minimal recessive bit time trec(min) 80 96 113 s Maximum recessive bit time trec(max) 80 96 113 s 21.01 Duty cycle 1 D3 D3 = trec(min) / (2*tBit) 0.417 A 21.02 Duty cycle 2 D4 D4 = trec(max) / (2*tBit) 0.590 A LIN transceiver parameter according to SAE J2602 (10.4kbit/s) Conditions: Low slew mode; VS =7.0V to 18V; LIN loads: 1k /1nF;660/6.8nF;500/10nF TxD signal: tBit = 96µs, twH = TwL = tBit; trise = tfall < 100ns 22.01 Minimal recessive delay TxD -> LIN tx_rec_min 48 s A 22.02 Maximum recessive delay TxD -> LIN tx_rec_max 48 s A 22.03 Minimal dominant delay TxD -> LIN tx_dom_min 48 s A 22.04 Maximum dominant delay TxD -> LIN tx_dom_max 48 s A 22.05 Maximum rec. to dom. delay Tr_d_max tx_rec_max - tx_dom_min 15.9 s A 22.06 Maximum dom. to rec. delay Td_r_max tx_dom_max - tx_rec_min 17.2 s A Notes: [1] A = 100% serial test, B = Operating parameter, C = characterization data, D = Value guaranteed by design |
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