UCS1001 datasheet(40/59 Pages) MICROCHIP

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USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.2 (05-21-12)

SMSC UCS1001

DATASHEET

6.4

VBUS Discharge

The UCS1001 will discharge VBUS through an internal 100  resistor when at least one of the following

conditions occurs:



The PWR_EN control is disabled (triggered on the inactive edge of the PWR_EN control).



A portable device Removal Detection event is flagged.



The VS voltage drops below a specified threshold (VS_UVLO) that causes the port power switch to

be disabled.



When commanded into the Sleep power state via the EM_EN, M1, and M2 controls.



Before each charger emulation profile is applied.



Upon recovery from the Error state.



Any time that the port power switch is activated after the VBUS bypass switch has been on (i.e.,

whenever VBUS voltage transitions from being driven from VDD to being driven from VS, such as

going from Detect to Active power state).



Any time that the VBUS bypass switch is activated after the port power switch has been on (i.e.,

going from Active to Detect power state).

When the VBUS discharge circuitry is activated, the UCS1001 will confirm that VBUS was discharged.

If the VBUS voltage is not below the VTEST level, a discharge error will be flagged and the UCS1001

will enter the Error state.

6.5

Fault Handling Mechanism

The UCS1001 has two modes for handling faults: Latch (latch-upon-fault) or Auto-recovery

(automatically attempt to restore the Active power state after a fault occurs). The fault handling

mechanism used depends on the state of the LATCH pin. Faults include over-current, over-voltage (on

VS), under-voltage (on VBUS), back-voltage (VBUS to VS or VBUS to VDD), discharge error, and

maximum allowable internal die temperature (TTSD) exceeded (see Section 4.1.5, "Error State

Operation").

6.5.1

Auto-recovery Fault Handling

When the LATCH pin is low, auto-recovery fault handling is used. When an error condition is detected,

the UCS1001 will immediately enter the Error state and assert the ALERT# pin (see Section 4.1.5).

Independently from the host controller, the UCS1001 will wait a preset time (tCYCLE), check error

conditions (tTST), and restore Active operation if the error condition(s) no longer exist. The ALERT#

pin will be released.

6.5.2

Latched Fault Handling

When the LATCH pin is high, latch fault handling is used. When an error condition is detected, the

UCS1001 will enter the Error power state and assert the ALERT# pin. Upon command from the host

controller (by toggling the PWR_EN pin from enabled to disabled), the UCS1001 will check error

conditions once and restore Active operation if error conditions no longer exist. If an error condition

still exists, the host controller is required to issue the command again to check error conditions.

UCS1001 Datasheet(PDF) 40 Page - Microchip Technology

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