ADE7754ARRL datasheet(10/44 Pages) AD

10 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 10 –

POWER SUPPLY MONITOR

The ADE7754 also contains an on-chip power supply moni-

tor. The Analog Supply (AVDD) is continuously monitored

by the ADE7754. If the supply is less than 4V ± 5% then the

ADE7754 will go in an inactive state, i.e. no energy will be

accumulated when the supply voltage is below 4V. This is

useful to ensure correct device operation at power up and

during power down. The power supply monitor has built-in

hysteresis and filtering. This gives a high degree of immunity

to false triggering due to noisy supplies.

Time

AVDD

ADE7754

Power-on

Inactive

Active

Inactive

RESET flag in the

Interrupt Status register

Read RSTATUS register

Figure 2 - On chip Power supply monitoring

The RESET bit in the Interrupt Status register is set to logic

one when AVDD drops below 4V ± 5%. The RESET flag is

always masked by the Interrupt Mask register and cannot

cause the IRQ pin to go low. The Power supply and

decoupling for the part should be such that the ripple at

AVDD does not exceed 5V ± 5% as specified for normal

operation.

ANALOG INPUTS

The ADE7754 has a total of six analog inputs, dividable into

two channels: current channel and voltage channel. The

current channel consists of three pairs of fully-differential

voltage inputs, namely (IAP, IAN; IBP, IBN; ICP, ICN). The fully

differential voltage input pairs have a maximum differential

voltage of ±0.5V. The voltage channel has three single-ended

voltage inputs VAP, VBP, and VCP. These single-ended volt-

age inputs have a maximum input voltage of ±0.5V with

respect to VN. Both the current channel and the voltage

channel have a PGA (Programmable Gain Amplifier) with

possible gain selections of 1, 2, or 4. The same gain is applied

to all the inputs of each channel.

The gain selections are made by writing to the Gain register.

Bits 0 to 1 select the gain for the PGA in the fully-differential

current channel. The gain selection for the PGA in the single-

ended voltage channel is made via bits 5 to 6. Figure 3 shows

how a gain selection for the current channel is made using the

Gain register.

IAP, IBP, ICP

IAN, IBN, ICN

Vin

k·Vin

GAIN[7:0]

Gain (k)

selection

Figure 3— PGA in current channel

Figure 4 shows how the gain settings in PGA 1 (current

channel) and PGA 2 (voltage channel) are selected by various

bits in the Gain register. The no load threshold and sum of

the absolute value can also be selected in the Gain register -

see Table X.

GAIN REGISTER*

current & voltage Channel PGA Control

ADDR: 18h

PGA 2 Gain Select

00 = x1

01 = x2

10 = x4

*Register contents show power on defaults

PGA 1 Gain Select

00 = x1

01 = x2

10 = x4

RESERVED

RESERVED=0

ABS

Load

Figure 4 — ADE7754 Analog Gain register

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