ADE7754ARRL datasheet(30/44 Pages) AD

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REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 30 –

The total apparent power calculated by the ADE7754 in the

Line accumulation mode depends on the configuration of the

VAMOD bits in the VAMode register. Each term of the

formula can be disabled or enabled by the LVASEL bits of

the VAMode register. The different configurations are de-

scribed in Table VI.

VA-

VASEL0

VASEL1

VASEL2

MOD

VArms x IArms + VBrms x IBrms

+ VCrms x ICrms

VArmsxIArms

+(VArms+VCrms)/2xIBrms + VCrms x ICrms

VArms x IArms + VArms x IBrms

+ VCrms x ICrms

Table VI -Total Line Apparent Energy calculation

The Line Apparent Energy accumulation uses the same

signal path as the Apparent Energy accumulation. The LSB

size of these two registers is equivalent.

The ADE7754 accumulates the Total Reactive Power signal

in the LAENERGY register. This mode is selected by setting

to logic one bit5 of the WAVMode register (Add. 0Ch).

When this bit is set the accumulation of the Active Energy

over half line cycles in the LAENERGY register is disabled

and is done instead in the LVAENERGY register. In this

mode, the accumulation of the Apparent Energy over half line

cycles in the LVAENERGY is no-longer available - see

Figure 31. As the LVAENERGY register is an unsigned

value, the accumulation of the active energy in the

LVAENERGY register is unsigned. In this mode (reactive

energy), the selection of the phases accumulated in the

LAENERGY and LVAENERGY registers is done by the

LWATSEL selection bits of the WATMode register.

ENERGIES SCALING

The ADE7754 provides measurements of the Active, Reac-

tive and Apparent energies. These measurements do not have

the same scaling and cannot be compared directly to each

others.

When measuring the different energies with the ADE7754

with 50Hz signals at different power factor, the ratio between

the energies is:

PF=1

PF=0.707

PF=0

Active

W h

Wh x 0.707

Energy

Reactive

Wh x 0.707 / 9.546

Wh / 9.546

Energy

Apparent Wh / 3.657

Wh / 3.657

Energy

CHECK SUM REGISTER

The ADE7754 has a check sum register (CHECKSUM[5:0])

to ensure the data bits received in the last serial read

operation are not corrupted. The 6-bit Checksum register is

reset before the first bit (MSB of the register to be read) is

put on the DOUT pin. During a serial read operation, when

each data bit becomes available on the rising edge of SCLK,

the bit will be added to the Checksum register. In the end of

the serial read operation, the content of the Checksum

previously read. Using the Checksum register, the user can

determine if an error has occurred during the last read

operation.

Note that a read to the Checksum register will also generate

a checksum of the Checksum register itself.

CONTENT OF REGISTER (n-bytes)

DOUT

CHECKSUM REGISTER ADDR: 3EH

Figure 38 - Checksum register for Serial Interface Read

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