SEC1110 datasheet(21/218 Pages) MICROCHIP

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 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 21

SEC1110/SEC1210

7.1.1

EC DATA MEMORY

The EC has 1.5 KB data memory that is accessed through the XDATA Bus which is implemented with static RAM and

organized as 1.5 K x 8 bits. The base address of the memory is 8000h in the EC address space and extends to location

85FFh.

7.1.2

EC OTP INSTRUCTION MEMORY

The primary instruction memory for the EC is a 16 Kx 8 bit OTP ROM memory, located at locations 0000h through 3FFFh

in the EC address space. There is also a 4 K x 8 bit ROM that is used to overlay the OTP memory when it has not been

programmed. A bit in the OTP disables the ROM overlay. The OTP memory is also mapped into the XDATA space when

the overlay is active so that the CPU can program the OTP from the USB bus.

7.2

EC Registers

The truth table indicates which memory is mapped into the 8051 CODE space depending on the three signals ROM_EN,

defined in the OTP_CFG Register. OTP_ROM_EN, and the EXT_SPI_EN (BOND2 bond option).

7.3

EC Memory Map

TABLE 7-1:

CODE EXECUTION TRUTH TABLE

OTP_CFG.FORCE_OTP_ROM

OTP_CFG.OTP_ROM_EN

EXT_SPI_EN/

BOND[2]

CODE

EXECUTION

External SPI2

ROM

OTP

TABLE 7-2:

CODE SPACE

Name

Address Range

INTERNAL ROM (4 K) (SEC1110 and SEC1210)

INTERNAL ROM (16 K) (later versions)

0000h-0FFFh

C000h-CFFFh (alias address range) (deprecated)

18000h-18FFFh (alias address range)

1A000h-1DFFFh (alias address range) (later

versions)

OTP ROM (16 K)

0000h-3FFFh

EXTERNAL SPI

0000-FFFFh

SRAM (1.5 K)

19000h-195FFh (alias address range)

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