MCP652 datasheet(26/62 Pages) MICROCHIP

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MCP651/1S/2/3/4/5/9

DS20002146D-page 26

 2009-2014 Microchip Technology Inc.

EQUATION 4-7:

The maximum ambient to junction temperature rise

(

TJA) and junction temperature (TJ) can be calculated

using the maximum expected package power (PPKG),

ambient temperature (TA) and the package thermal

resistance (

JA) found in Table 1-4:

EQUATION 4-8:

The worst-case power de-rating for the op amps in a

particular package can be easily calculated:

EQUATION 4-9:

Several techniques are available to reduce

TJA for a

given package:

• Reduce

JA

- Use another package

- Improve the PCB layout (ground plane, etc.)

- Add heat sinks and air flow

• Reduce max(PPKG)

- Increase RL

- Decrease CL

- Limit IOUT using RISO (see Figure 4-9)

- Decrease VDD

4.4

Improving Stability

4.4.1

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. See Figure 2-30. A unity-gain buffer

(G = +1) is the most sensitive to capacitive loads,

though all gains show the same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 20 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-9) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-9:

Output Resistor, RISO

Stabilizes Large Capacitive Loads.

Figure 4-10 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN =+2V/V).

FIGURE 4-10:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify RISO’s value until the

response is reasonable. Bench evaluation and

simulations with the MCP651/1S/2/3/4/5/9 SPICE

macro model are helpful.

4.4.2

GAIN PEAKING

Figure 4-11 shows an op amp circuit that represents

non-inverting amplifiers (VM is a DC voltage and VP is

the input) or inverting amplifiers (VP is a DC voltage

and VM is the input). The capacitances CN and CG

represent the total capacitance at the input pins; they

include the op amp’s Common mode input capacitance

(CCM), board parasitic capacitance and any capacitor

placed in parallel.

PK G



Where:

n = Number of op amps in package (1 or 2)

T

PKGJA

T

PKG

Jmax

–



--------------------------



Where:

TJmax = Absolute maximum junction

temperature (°C)

TA = Ambient temperature (°C)

RISO

VOUT

MCP65X

100

1.E-11

1.E-10

1.E-09

1.E-08

Normalized Capacitance; CL/GN (F)

GN = +1

GN  +2

10p

100p

10n

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