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IXDD415SI

IXYS Semiconductor GmbH

Edisonstrasse15 ; D-68623; Lampertheim

Tel: +49-6206-503-0; Fax: +49-6206-503627

e-mail: marcom@ixys.de

IXYS Corporation

3540 Bassett St; Santa Clara, CA 95054

Tel: 408-982-0700; Fax: 408-496-0670

e-mail: sales@ixys.net

www.ixys.com

Directed Energy, Inc.

An IXYS Company

2401 Research Blvd. Ste. 108, Ft. Collins, CO 80526

Tel: 970-493-1901; Fax: 970-493-1903

e-mail: deiinfo@directedenergy.com

www.directedenergy.com

The enable (EN) input to the IXDD415 is a high voltage

CMOS logic level input where the EN input threshold is ½ V

and may not be compatible with 5V CMOS or TTL input levels.

The IXDD415 EN input was intentionally designed for

enhanced noise immunity with the high voltage CMOS logic

levels. In a typical gate driver application, V

EN input threshold at 7.5V, a 5V CMOS logical high input

applied to this typical IXDD415 application’s EN input will be

misinterpreted as a logical low, and may cause undesirable

or unexpected results. The note below is for optional

adaptation of TTL or 5V CMOS levels.

The circuit in Figure 16 alleviates this potential logic level

misinterpretation by translating a TTL or 5V CMOS logic input

to high voltage CMOS logic levels needed by the IXDD415 EN

input. From the figure, V

typically set between 8V to 20V, and V

supply, typically between 3.3V to 5.5V. Resistors R1 and R2

form a voltage divider network so that the Q1 base is posi-

tioned at the midpoint of the expected TTL logic transition

levels.

A TTL or 5V CMOS logic low, V

the Q1 emitter will drive it on. This causes the level translator

output, the Q1 collector output to settle to V

V

interpreted as a high voltage CMOS logic low (<1/3V

V

A TTL high, V

V

Figure 16 will cause Q1 to be biased off. This results in Q1

collector being pulled up by R3 to V

high voltage CMOS logic high output. The high voltage CMOS

logical EN output applied to the IXDD415 EN input will enable

it, allowing the gate driver to fully function as a 15 Ampere

output driver.

The total component cost of the circuit in Figure 16 is less

than $0.10 if purchased in quantities >1K pieces.

It is

recommended that the physical placement of the level

translator circuit be placed close to the source of the TTL or

CMOS logic circuits to maximize noise rejection.

TTL to High Voltage CMOS Level Translation

10K

R3

3.3K

R2

Q1

2N3904

EN

Output

CC

(From Gate Driver

Power Supply)

Input)

TTL

CMOS

3.3K

R1

(From Logic

Power Supply)

or

High Voltage

(To IXDD415

EN Input)

Figure 16 - TTL to High Voltage CMOS Level Translator

Doc #9200-0233 R2