LMV921 datasheet(30/42 Pages) NSC

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3-1

LMV921 Qualification Package

3.0 PROCESS INFORMATION

3.1 Process Details

Fabrication Site: South Portland Fairchild

Process Technology: CS80CBI (Submicron Silicon Gate CMOS/Bipolar)

Minimum Feature Size: 0.8 microns

Wafer Diameter: 6 inches

Number of Masks: 18

Metallization: 0.5% Copper, dual layer Aluminum metal

1st layer = 7,500 Å thick

2nd layer = 12,000 Å thick

Top Side Passivation: Over Nitride (11,500 Å thick)

Over Oxide (5,000 Å thick)

3.2 Process Detail & Masks

STAGE 1:

Initial Ox

STAGE 2:

Trench Define & Etch

STAGE 3:

Mask 0.6, N-Iso

STAGE 4:

N-Iso Implant

STAGE 5:

N-Iso Drive

STAGE 6:

N-Iso Ox Strip & Screen Ox

STAGE 7:

Mask 0.8, N+ Buried layer

STAGE 8:

N+ Buried Layer Implant

STAGE 9:

Mask 0.9,P+ Buried Layer

STAGE 10:

P+ Buried Layer Implant

STAGE 11:

Buried Layer Anneal

STAGE 12:

Epi Growth

STAGE 13:

Pad Oxide & Nitride

STAGE 14:

Mask 1.0, N-Well

STAGE 15:

N-Well Implant

STAGE 16:

Selective Oxide

STAGE 17:

N-Well Nitride Strip

STAGE 18:

P-Well implant

STAGE 19:

Selective Oxide Etch

STAGE 20:

N-Well & P-Well Drive-In Oxide

STAGE 21:

Drive-In Oxide Strip

STAGE 22:

Mask 2.0, Composite

STAGE 23:

Composite Pad Oxide & Composite Nitride

STAGE 24:

Composite Mask Etch

STAGE 25:

Mask 3.0, P-Field

STAGE 26:

P-Field Implant

STAGE 27:

Iso Field Oxide

STAGE 28:

Active (Composite Area) Nitride Strip

STAGE 29:

Pad Oxide Removal & Sacrificial Oxide Growth & Vt Adjust Implant

STAGE 30:

Sacrificial Oxide Strip & Gate Oxide & Poly Deposition

LMV921 Datasheet(PDF) 30 Page - National Semiconductor (TI)

LMV921 Datasheet(HTML) 30 Page - National Semiconductor (TI)

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