Bit

Description

Comment

15

Codec Ready

Bit

0=Not Ready, 1=Ready

14

Slot 1 data

valid

Status Address is valid

13

Slot 2 data

valid

Status Data is valid

12

Slot 3 data

valid

Left Audio PCM Data is

valid

11

Slot 4 data

valid

Right Audio PCM Data is

valid

SD_IN Slot 1: Status Address

The slot echoes the control register which a read was re-

quested on. The address echoed was initiated by a read re-

quest in the previous SD_OUT frame, slot 1.

Bits

Description

Comment

19

Reserved

Stuffed with

″0″

18:12

Control

Register Index

Echo of Control Register

for which data is being

returned.

11:0

Reserved

Stuffed with

″0″ ’s

SD_IN Slot 2: Status Data

The slot returns the control register data. The data returned

was initiated by a read request in the previous SD_OUT

frame, slot 1.

Bits

Description

Comment

19:4

Control

Register Read

Data

3:0

Reserved

Stuffed with

″0″ ’s

SD_IN Slot 3: PCM Record Left Channel

This slot contains the left ADC sample data. The signal digi-

tized is selected via register 1Ah and subsequently routed

through the Input Mux for recording by the left ADC.

Bits

Description

Comment

19:2

PCM Record

Left Channel

data

18 bit audio sample from

left ADC

Bits

Description

Comment

1:0

Reserved

Stuffed with

″0″’s

SD_IN Slot 4: PCM Record Right Channel

This slot contains the right ADC sample data. The signal digi-

tized is selected via register 1Ah and subsequently routed

through the Input Mux for recording by the right ADC.

Bits

Description

Comment

19:2

PCM Record

Right Channel

data

18 bit audio sample from

right ADC

1:0

Reserved

Stuffed with

″0″’s

SD_IN Slots 5-12: Reserved

These SD_IN slots are set to

″0″ as they are reserved for fu-

ture use.

AC Link Low Power Mode

Reset Register (00h)

Writing any value to this register causes a register reset

which changes all of the registers back to their default val-

ues. If this register is read, the codec will return a value of

0D50h indicating that National 3D Sound is implemented

and 18 bit data is supported by both the ADCs and DACs.

Master Volume Registers (02h, 06h)

These registers allows the output levels from LINE_OUT port

and MONO_OUT port to be attenuated or muted. Each step

is nominally 1.5dB and each output can be individually

muted by setting the most significant bit to 1.

Mute

Mx5:Mx0

Function

0

00 0000

0dB attenuation

0

01 1111

46.5dB attenuation

0

1X XXXX

46.5dB attenuation

1

XX XXXX

mute

Default: 8000h

PC Beep Register (0Ah)

This register controls the level of the PC_BEEP input. The

PC_BEEP can be both attenuated and muted via register

0Ah. Step size is nominally 3dB. The signal present after the

attenuation and mute block is summed into both the left and

right channels.

Mute

PV3:0

Function

0

0000

0dB attenuation

0

1111

45dB attenuation

1

XXXX

mute

Default: 8000h

DS100907-7

FIGURE 7. Start of Audio Input Frame

DS100907-9

FIGURE 8. AC Link Powerdown Timing

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