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IMP16C554 Datasheet(PDF) 5 Page - IMP, Inc

Part # IMP16C554
Description  Quad Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
PDF  20 Pages
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Manufacturer  IMP [IMP, Inc]
Direct Link  http://www.ds-imp.com.cn/index.asp
Logo IMP - IMP, Inc

IMP16C554 Datasheet(HTML) 5 Page - IMP, Inc

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IMP16C554 ACCESSIBLE REGISTERS
A2A1A0
Registe
r
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0 0 0
RHR
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0 0 0
THR
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0 0 1
IER
0
0
0
0
Modem
status
interrup
t
Receiv
e
line
status
interru
pt
Transmi
t
holding
register
Receive
holding
register
0 1 0
FCR
RCV
R
trigge
r
(MSB
)
RCV
R
trigge
r
(LSB)
0
0
DMA
Mode
select
XMITF
IFO
reset
RCVRF
IFO
reset
FIFO
enable
0 1 0
ISR
0/FIF
Os
enabl
ed
0/FIF
Os
enabl
ed
0
0
int
priority
bit-2
Int
priority
bit-1
Int
priority
bit-0
Int
status
0 1 1
LCR
Divis
or
latch
enabl
e
Set
break
Set
parity
Even
parity
Parity
enable
Stop
bits
Word
length
bit-1
Word
length
bit-0
1 0 0
MCR
0
0
0
Loop
back
INT
enable
Not
used
RTS*
DTR*
1 0 1
LSR
o/FIF
O
error
trans
empt
y
trans
holdi
ng
empt
y
break
interr
upt
framing
error
parity
error
overrun
error
receive
data
ready
1 1 0
MSR
CD
RI
DSR
CTS
delta
CD*
delta
RI*
delta
DSR*
delta
CTS*
1 1 1
SPR
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0 0 0
DLL
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0 0 1
DLM
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
DLL and DLM are accessible only when LCR bit-7 is set to “1”.
5
408-432-9100/www.impweb.com
© 2002 IMP, Inc.
IMP16C554
IMP16C554



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