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MXAPM3A5-BRF-001-A M03-0778

© 2003 Mindspeed Technologies, Inc. All rights reserved. Mindspeed and the Mindspeed

logo are trademarks of Mindspeed Technologies. All other trademarks are the property

of their respective owners. Although Mindspeed Technologies strives for accuracy in all

its publications, this material may contain errors or omissions and is subject to change

without notice. This material is provided as is and without any express or implied

warranties, including merchantability, fitness for a particular purpose and

non-infringement. Mindspeed Technologies shall not be liable for any special, indirect,

incidental or consequential damages as a result of its use.

Functions

• ITU I.363.5 AAL5 SAR

• Up to OC-48c throughput

• A maximum of 256K connections

• Supports up to 64 PHYs at 64 different rates

• Traffic shaping – dual GCRA per connection

• Supports the following traffic shaping

conformance definitions:

- CBR.1, VBR.1 (rt, nrt), UBR.1, UBR.2, UBR+

• VP tunnels with WRR access

• VC tunnels with CBWFQ access

• Congestion control

- WRED, per VC flow control, per VC EPD

• ATM-to-MPLS interworking based

on ietf-pwe3-atm-encap

• Reassembly time-out

• Encapsulation / de-encapsulation

• Support for raw cells (AAL0)

• Integrated OAM cell processing

• Ingress policing

• Auto-VC discovery

• Host control via PCI bus

• Per-connection and per-port statistics

See the TSP3 traffic stream processor

data sheet for a description of the hardware

interfaces, memory requirements, and device

characteristics.

Product Features

The WRED algorithm discards packets in a manner that optimizes the

overall network performance of TCP/IP connections. Up to 128 sets of

WRED parameters are supported, selected on a per packet basis. The

per-VC flow control option sends indications to the host when a config-

urable high and low threshold are crossed (with hysteresis). Per-VC EPD

is similar to flow control except that packets are dropped when the

high threshold is exceeded, and no indications are sent.

Both the segmenter and reassembler provide per-buffer-class EPD

when a configurable threshold is exceeded, and partial packet discard

(PPD) when the buffer class is exhausted.

VP Tunnels with Weighted Round Robin

A segmenter VP tunnel consists of a group of VCs, each of which

gains access to the tunnel using a weighted round robin scheme.

This allows proportional bandwidth sharing among the VCs. The

tunnel itself is then shaped in the same manner as ordinary VCs.

Up to 32K VP tunnels are supported.

VC Tunnels with Class Based Weighted Fair Queuing

A segmenter VC tunnel provides up to eight class of service (CoS)

queues, allowing packets from each CoS queue to be multiplexed

onto a single channel. The CoS queues are serviced using a class-

based weighted fair queuing (CBWFQ) algorithm with a low latency-

mode. Fairness is measured on a per-cell basis, however, full packets

are transmitted at a time. The tunnel itself is then shaped in the

same manner as ordinary VCs. Up to 32K VC tunnels, each with 8 CoS

queues, are supported.

ATM-to-MPLS Interworking

PortMakerIII supports ietf-pwe3-atm-encap (draft-martini) and can be

run concurrently with AAL5 segmentation-and-reassembly channels,

selectable on a per channel basis.

This cell-bundling function provides the basis of interworking ATM-to-

MPLS in order to provide efficient transport of ATM over an IP/MPLS

network core. For cell bundling, ATM cells are received, header transla-

tion is performed, and a configurable number of cells are bundled into

an MPLS packet. For bundling, MPLS packets are received on egress,

ATM cells are unbundled individually from the packet, and traffic

management criteria are then applied for the channel. Timers are

used to control latency during bundle creation.

Encapsulation / De-encapsulation

The segmenter offers optional 8- or 10-byte encapsulation, supporting

routed IPv4 and bridged Ethernet PDUs as defined in RFC 2684/1483.

The reassembler offers optional stripping of up to 31 bytes. All encap-

sulation and de-encapsulation parameters are determined on a per

channel basis. Other formats can be readily supported.

Applications

The PortMakerIII firmware is intended for use in enterprise, aggregation,

edge and core routers, multi-service edge switches, optical edge

equipment, DSLAMs, and fixed and mobile wireless equipment. A typical

OC-48 application using two M27483 devices running PortMakerIII is

shown below.

Figure 1: Bi-directional OC-48

System

Line

Host

Processor

Input System Port 0

Line Egress Port 0

Line Egress Port 1

Line Egress Port 63

Line Egress Port 63

System Ingress Port 0

System Ingress Port 3

Line Egress Port 0

Line Egress Port 1

URX0

UTX0

UTX0

URX0

PCI

PCI

Input/Output

System Port

M27483

M27483

AAL5 Segmentation

AAL5 Reassembly

Input/Output

System Port

(PHY)

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System Egress