DS1482

7 of 7

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

OUTPUT PIN RXD

Output-Low Voltage

100µA load

0.4

V

Output-High Voltage

-100µA load

V

Output Rise Time

(50pF Load)

50

ns

Output Fall Time

(50pF Load)

50

ns

Delay I/O to RXD

(50pF Load)

See Figure 6 (Note 2)

100

ns

OUTPUT PIN PCTLZ

Output-Low Voltage

100µA load

0.4

V

Output-High Voltage

-100µA load

V

Output Rise Time

(50pF Load)

50

ns

Output Fall Time

(50pF Load)

50

ns

Delay SPU to PCTLZ

(50pF Load)

See Figure 7 (Note 4)

100

ns

OUTPUT PIN DONE

Output-Low Voltage

100µA load

0.4

V

Output-High Voltage

-100µA load

V

Output Rise Time

(50pF Load)

50

ns

Output Fall Time

(50pF Load)

50

ns

Delay I/O to DONE

(50pF Load)

128

500

µs

Delay START to

DONE (50pF Load)

See Figure 8

100

ns

Note 1:

The input pins have a weak pulldown.

Note 2:

For OD read- or write-1 time slots, TXD should be pulsed high for 1.28µs. The window for

sampling RXD begins 1.8µs after TXD has turned high and ends 2.05µs after TXD has turned

high. RXD must be sampled inside this window. Correct sampling can be achieved with the

particular recommended microcontroller Hitachi SH7622 if the peripheral module operating

frequency P

F is higher or equal to 22MHz.

Note 3:

parameter is guaranteed by design, and is not production tested.

Note 4:

The PCTLZ signal is gated by TXD. The PCTLZ output is only low if TXD is low.

Note 5:

Characteristic of the glitch-eating filter on the output of the load-sensing comparator, i.e., an

event where the downstream 1-Wire slave device is sinking high current, ceases sinking the

current for less than this amount of time, and resumes sinking the current does not generate

high level on DONE; DONE goes high this amount of time after the downstream 1-Wire slave

device has ceased sinking high current.