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DS5001FP Datasheet(PDF) 13 Page - Dallas Semiconductor

Part # DS5001FP
Description  128k Soft Microprocessor Chip
PDF  26 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS5001FP Datasheet(HTML) 13 Page - Dallas Semiconductor

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DS5001FP
13 of 26
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
(TA = 0°C to +70°C; VCC = 5V ±10%)
#
PARAMETER
SYMBOL
MIN
MAX
UNITS
1
Oscillator Frequency
1/ tCLK
1.0
16
MHz
2
ALE Pulse Width
tALPW
2tCLK - 40
ns
3
Address Valid to ALE Low
tAVALL
tCLK - 40
ns
4
Address Hold After ALE Low
tAVAAV
tCLK - 35
ns
5
ALE Low to Valid Instruction In
at 12MHz
at 16MHz
tALLVI
4tCLK - 150
4tCLK - 90
ns
ns
6
ALE Low to PSEN Low
tALLPSL
tCLK - 25
ns
7
PSEN
Pulse Width
tPSPW
3tCLK - 35
ns
8
PSEN
Low to Valid Instruction In
at 12MHz
at 16MHz
tPSLVI
3tCLK - 150
3tCLK - 90
ns
ns
9
Input Instruction Hold After PSEN Going
High
tPSIV
0ns
10
Input Instruction Float After PSEN Going
High
tPSIX
tCLK - 20
ns
11
Address Hold After PSEN Going High
tPSAV
tCLK - 8
ns
12
Address Valid to Valid Instruction In
at 12MHz
at 16MHz
tAVVI
5tCLK - 150
5tCLK - 90
ns
ns
13
PSEN
Low to Address Float
tPSLAZ
0ns
14
RD
Pulse Width
tRDPW
6tCLK - 100
ns
15
WR
Pulse Width
tWRPW
6tCLK - 100
ns
16
RD
Low to Valid Data In
at 12MHz
at 16MHz
tRDLDV
5tCLK - 165
5tCLK - 105
ns
ns
17
Data Hold After RD High
tRDHDV
0ns
18
Data Float After RD High
tRDHDZ
2tCLK - 70
ns
19
ALE Low to Valid Data In
at 12MHz
at 16MHz
tALLVD
8tCLK - 150
8tCLK - 90
ns
20
Valid Address to Valid Data In
at 12MHz
at 16MHz
tAVDV
9tCLK - 165
9tCLK - 105
ns
21
ALE Low to RD or WR Low
tALLRDL
3tCLK - 50
3tCLK + 50
ns
22
Address Valid to RD or WR Low
tAVRDL
4tCLK - 130
ns
23
Data Valid to WR Going Low
tDVWRL
tCLK - 60
ns
24
Data Valid to WR High
at 12MHz
at 16MHz
tDVWRH
7tCLK - 150
7tCLK - 90
ns
25
Data Valid After WR High
tWRHDV
tCLK - 50
ns
26
RD
Low to Address Float
tRDLAZ
0ns
27
RD
or WR High to ALE High
tRDHALH
tCLK - 40
tCLK + 50
ns



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