SI596 datasheet(2/12 Pages) SILABS

2 / 12 page

Si596

Rev. 1.0

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Supply Voltage1

VDD

3.3 V option

2.97

3.3

3.63

2.5 V option

2.25

2.5

2.75

1.8 V option

1.71

1.8

1.89

Supply Current

IDD

LVPECL

CML

LVDS

CMOS

—

120

110

100

135

120

110

100

Frequency Select (FS)2

VIH

0.75 x VDD

——

VIL

——

0.5

Operating Temperature Range

–40

—

°C

Notes:

1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 7 for further details.

2. FS pin includes an internal 17 k

 pullup resistor to V

DD. When the FS is left floating, the pullup causes

FS = 1 = second frequency selected.

Table 2. VC Control Voltage Input

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Control Voltage Tuning Slope1,2,3

10 to 90% of VDD

—45

125

185

380

—

ppm/V

Control Voltage Linearity4

LVC

BSL

–5

±1

Incremental

–10

±5

+10

Modulation Bandwidth

9.3

10.0

10.7

kHz

VC Input Impedance

ZVC

500

—



VC Input Capacitance

CVC

—50

—

Nominal Control Voltage

VCNOM

@ fO

—VDD/2

—

Control Voltage Tuning Range

0VDD

Notes:

1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 7.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. KV variation is ±10% of typical values.

4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope

determined with VC ranging from 10 to 90% of VDD.

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