SL28PCIe50

DOC#: SP-AP-0758 (Rev. AA)

Page 2 of 16

32-QFN Pin Definitions

Pin No.

Name

Type

Description

1

VSS_PCI

GND

Ground for PCI clock

2

VDD_PCI

PWR 3.3V, Power Supply for PCI clock

3

CLKREQ#3*

I, PU

3.3V, active low input clock request to enable SRC3

(internal 100k-ohm internal pull-up)

4

CLKREQ#4*

I, PU

3.3V, active low input clock request to enable SRC4

(internal 100k-ohm internal pull-up)

5

CLKREQ#5*

I, PU

3.3V, active low input clock request to enable SRC5

(internal 100k-ohm internal pull-up)

6

VDD_SE2

PWR 3.3V, Power Supply for CONF_SE2 clock

7

CONF_SE2

O, SE 3.3V, configurable single-ended clock

8

VSS_SE2

GND

Ground for SE2 clock

9

OE_REF0

I

3.3V, active high input pin to enabled REF0

10

OE_REF1

I

3.3V, active high input pin to enabled REF1

11

VSS_SRC

GND

Ground for SRC clocks

12

OE_REF2

I

3.3V, active high input pin to enabled REF2

13

OE_CONF_SE2

I

3.3V, active high input pin to enabled CONF_SE2

14

VDD_SRC

PWR 3.3V Power Supply for SRC clocks

15

SRC1

O, DIF 100MHz True differential serial reference clock

16

SRC1#

O, DIF 100MHz Complement differential serial reference clock

17

SRC2

O, DIF 100MHz True differential serial reference clock

18

SRC2#

O, DIF 100MHz Complement differential serial reference clock

19

SRC3

O, DIF 100MHz True differential serial reference clock

20

SRC3#

O, DIF 100MHz Complement differential serial reference clock

21

VSS_SRC

GND

Ground for SRC clocks

22

VDD_SRC_IO

PWR Scalable 3.3V to 1.05V Power supply for SRC clocks

23

VSS_SRC

GND

Ground for SRC clocks

24

VDD_SRC_IO

PWR Scalable 3.3V to 1.05V Power supply for SRC clocks

25

SRC4#

O, DIF 100MHz Complement differential serial reference clock

26

SRC4

O, DIF 100MHz True differential serial reference clock

27

VDD_SRC

PWR 3.3V, Power Supply for SRC clocks

28

SRC5#

O, DIF 100MHz Complement differential serial reference clock

29

SRC5

O, DIF 100MHz True differential serial reference clock

30

VSS_SRC

GND

Ground for SRC clocks

31

SCLK

I

SMBus compatible SCLOCK

32

SDATA

I/O

SMBus compatible SDATA

33

NC

NC

No Connect

34

SRC_EN

I

3.3V, active high input for master enable for all SRC clocks. When set to low, all

SRC clocks will be disabled regardless of CLKREQ state.

35

XOUT

O, SE 25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input)

36

XIN / CLKIN

I

25.00MHz Crystal input or 3.3V, 25MHz Clock Input

37

VSS_REF

GND

Ground for REF clocks

38

REF2

O, SE 3.3V, 25MHz reference output clock

39

REF1

O, SE 25MHz reference output clock

40

REF0

O, SE 25MHz reference output clock

41

VDD_REF

PWR 3.3V, Power Supply for REF clock and power to support WOL