TMS27C040 524288 BY 8-BIT UV ERASABLE

TMS27PC040 524288 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORY

SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997

2

POST OFFICE BOX 1443

description (continued)

The data outputs are 3-state for connecting multiple devices to a common bus

The TMS27C040 is offered in a 600-mil ceramic dual-in-line package (J suffix). The TMS27C040 is offered with

two choices of temperature ranges of 0

°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). (See Table 1.)

The TMS27PC040 is offered in a 32-lead plastic leaded chip carrier package ( FM suffix). The TMS27PC040

is offered with two choices of temperature ranges of 0

°C to 70°C (JL suffix) and –40°C to 85°C (JE suffix).

Table 1. Temperature Range Suffixes

FUNCTION

SUFFIX FOR OPERATING

FREE-AIR TEMPERATURE

RANGES

0

°C to 70°C

– 40

°C to 85°C

TMS27C040-XXX

JL

JE

TMS27PC040-XXX

FML

FME

These EPROMs and PROMS operate from a single 5-V supply ( in the read mode), and they are ideal for use

in microprocessor-based systems. One other (13 V) supply is needed for programming. All programming

signals are TTL level. For programming outside the system, existing EPROM programmers can be used.

operation

The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are

Table 2. Operation Modes

MODE

FUNCTION †

MODE

E

G

VPP

VCC

A9

A0

DQ0 – DQ7

Read

VIL

VIL

X

VCC

X

X

Data Out

Output Disable

VIL

VIH

VCC

VCC

X

X

Hi-Z

Standby

VIH

X

VCC

VCC

X

X

Hi-Z

Programming

VIL

VIH

VPP

VCC

X

X

Data In

Program Inhibit

VIH

VIH

VPP

VCC

X

X

Hi-Z

Verify

VIH

VIL

VPP

VCC

X

X

Data Out

Signature Mode

VIL

VIL

VCC

VCC

V ‡

VIL

MFG Code 97

Signature Mode

VIL

VIL

VCC

VCC

VH ‡

VIH

Device Code 50

† X can be VIL or VIH

‡ VH = 12 V ± 0.5 V

read / output disable

When the outputs of two or more TMS27C040s or TMS27PC040s are connected in parallel on the same bus,

the output of any particular device in the circuit can be read with no interference from competing outputs of the

other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other

devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.

latchup immunity

Latchup immunity on the TMS27C040 and TMS27PC040 is a minimum of 250 mA on all inputs and outputs.

This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM

is interfaced to industry standard TTL or MOS logic devices. The input / output layout approach controls latchup

without compromising performance or packing density.