P83C280 datasheet(33/84 Pages) PHILIPS

33 / 84 page

1997 Dec 12

Philips Semiconductors

Product speciﬁcation

Microcontrollers for monitors with DDC

interface, auto-sync detection and sync proc.

P83Cx80; P87C380

14.2.1

COARSE ADJUSTMENT

An active HIGH pulse is generated in every subperiod; the

pulse width being determined by the contents of PWM10H.

The coarse output (OUT1) is HIGH at the start of each

subperiod and will remain HIGH until the time

[4/fclk × (128 − PWM10H)] has elapsed. The output will

then go LOW and remain LOW until the start of the next

subperiod. The coarse pulse width may be calculated as:

14.2.2

FINE ADJUSTMENT

Fine adjustment is achieved by generating an additional

pulse in specific subperiods. The pulse is added at the

start of the selected subperiod and has a pulse width of

4/fclk. The contents of PWM10L determine in which

subperiods a fine pulse will be added. It is the logic 0 state

of the value held in PWM10L that actually selects the

subperiods. When more than one bit is a logic 1 then the

subperiods selected will be a combination of those

subperiods specified in Table 30.

Pulse duration

PWM10H

()

clk

-------

For example, if PWM10L = 000 0101 then this is a

combination of:

• PWM10L = 000 0001: subperiod 64

• PWM10L = 000 0100: subperiods 16, 48, 80 and 112.

Pulses will be added in subperiods 16, 48, 64, 80 and 112.

This example is illustrated in Fig.18.

When PWM10L holds 000 0000 fine adjustment is

inhibited and the PWM10 output is determined only by the

contents of PWM10H.

Table 30 Additional pulse distribution

PWM10L

ADDITIONAL PULSE IN SUBPERIOD

000 0001

000 0010

32 and 96

000 0100

16, 48, 80 and 112

000 1000

8, 24, 40, 56, 72, 88, 104 and 120

001 0000

4, 12, 20, 28, 36, 44, 52...116 and 124

010 0000

2, 6, 10, 14, 18, 22, 26, 30...122 and 126

100 0000

1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127

Fig.16 PWM10 output patterns: Coarse adjustment only.

handbook, full pagewidth

127

128

− (m + 1)

128

− (m − 1)

128

− m

127

decimal value PWM7H data latch

fclk

MGG045

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