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DS1375 Datasheet(PDF) 3 Page - Dallas Semiconductor |
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DS1375 Datasheet(HTML) 3 Page - Dallas Semiconductor |
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3 / 11 page ![]() 2-Wire Digital Input RTC with Alarm _____________________________________________________________________ 3 Note 8: After this period, the first clock pulse is generated. Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 10: The maximum tHD:DAT is only met if the device does not stretch the low period (tLOW) of the SCL signal. Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 12: CB—total capacitance of one bus line in pF. AC ELECTRICAL CHARACTERISTICS (VCC = VCCMIN to VCCMAX, TA = -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast mode 100 400 SCL Clock Frequency fSCL Standard mode 0 100 kHz Fast mode 1.3 Bus Free Time Between STOP and START Conditions tBUF Standard mode 4.7 µs Fast mode 0.6 Hold Time (Repeated) START Condition (Note 8) tHD:STA Standard mode 4.0 µs Fast mode 1.3 Low Period of SCL Clock tLOW Standard mode 4.7 µs Fast mode 0.6 High Period of SCL Clock tHIGH Standard mode 4.0 µs Fast mode 0 0.9 Data Hold Time (Notes 9, 10) tHD:DAT Standard mode 0 0.9 µs Fast mode 100 Data Setup Time (Note 11) tSU:DAT Standard mode 250 ns Fast mode 0.6 Start Setup Time tSU:STA Standard mode 4.7 µs Fast mode 300 Rise Time of Both SDA and SCL Signals (Note 12) tR Standard mode 20 + 0.1CB 1000 ns Fast mode 300 Fall Time of Both SDA and SCL Signals (Note 12) tF Standard mode 20 + 0.1CB 300 ns Fast mode 0.6 Setup Time for STOP Condition tSU:STO Standard mode 4.7 µs Capacitive Load for Each Bus Line (Note 12) CB 400 pF Pulse Width of Spikes that Must be Suppressed by the Input Filter tSP Fast mode 30 ns |
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