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18F452 Datasheet(PDF) 322 Page - Microchip Technology |
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18F452 Datasheet(HTML) 322 Page - Microchip Technology |
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322 / 332 page  PIC18FXX2 DS39564B-page 320 2002 Microchip Technology Inc. TBLRD ..................................................................... 249 TBLWT ..................................................................... 250 TSTFSZ .................................................................... 251 XORLW .................................................................... 251 XORWF .................................................................... 252 Summary Table ........................................................ 214 Instructions in Program Memory ........................................ 40 Two-Word Instructions ............................................... 41 INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register RBIF Bit ...................................................................... 90 INTCON Registers ....................................................... 75–77 Inter-Integrated Circuit. See I2C Interrupt Sources .............................................................. 195 A/D Conversion Complete ........................................ 184 Capture Complete (CCP) ......................................... 119 Compare Complete (CCP) ....................................... 120 INT0 ........................................................................... 85 Interrupt-on-Change (RB7:RB4 ) ............................... 90 PORTB, Interrupt-on-Change .................................... 85 RB0/INT Pin, External ................................................ 85 TMR0 ......................................................................... 85 TMR0 Overflow ........................................................ 105 TMR1 Overflow ................................................ 107, 109 TMR2 to PR2 Match ................................................. 112 TMR2 to PR2 Match (PWM) ............................ 111, 122 TMR3 Overflow ................................................ 113, 115 USART Receive/Transmit Complete ........................ 165 Interrupts ............................................................................ 73 Logic ........................................................................... 74 Interrupts, Enable Bits CCP1 Enable (CCP1IE Bit) ...................................... 119 Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) .................................. 183 CCP1 Flag (CCP1IF Bit) .......................................... 119 CCP1IF Flag (CCP1IF Bit) ....................................... 120 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ........................................................... 90 IORLW ............................................................................. 234 IORWF ............................................................................. 234 IPR Registers ............................................................... 82–83 K KEELOQ Evaluation and Programming Tools ................... 256 L LFSR ................................................................................ 235 Lookup Tables Computed GOTO ....................................................... 41 Table Reads, Table Writes ......................................... 41 Low Voltage Detect .......................................................... 189 Converter Characteristics ......................................... 267 Effects of a RESET .................................................. 193 Operation ................................................................. 192 Current Consumption ....................................... 193 During SLEEP .................................................. 193 Reference Voltage Set Point ............................ 193 Typical Application ................................................... 189 LVD. See Low Voltage Detect. ......................................... 189 M Master SSP (MSSP) Module Overview ........................... 125 Master Synchronous Serial Port (MSSP). See MSSP. Master Synchronous Serial Port. See MSSP Memory Organization Data Memory ............................................................. 42 Program Memory ....................................................... 35 Memory Programming Requirements .............................. 268 Migration from Baseline to Enhanced Devices ................ 314 Migration from High-End to Enhanced Devices ............... 315 Migration from Mid-Range to Enhanced Devices ............ 315 MOVF .............................................................................. 235 MOVFF ............................................................................ 236 MOVLB ............................................................................ 236 MOVLW ........................................................................... 237 MOVWF ........................................................................... 237 MPLAB C17 and MPLAB C18 C Compilers ..................... 253 MPLAB ICD In-Circuit Debugger ..................................... 255 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ....................................... 254 MPLAB Integrated Development Environment Software ............................................. 253 MPLINK Object Linker/MPLIB Object Librarian ............... 254 MSSP ............................................................................... 125 Control Registers (general) ...................................... 125 Enabling SPI I/O ...................................................... 129 Operation ................................................................. 128 Typical Connection .................................................. 129 MSSP Module SPI Master Mode ..................................................... 130 SPI Master./Slave Connection ................................. 129 SPI Slave Mode ....................................................... 131 MULLW ............................................................................ 238 MULWF ............................................................................ 238 N NEGF ............................................................................... 239 NOP ................................................................................. 239 O Opcode Field Descriptions ............................................... 212 OPTION_REG Register PSA Bit .................................................................... 105 T0CS Bit .................................................................. 105 T0PS2:T0PS0 Bits ................................................... 105 T0SE Bit ................................................................... 105 Oscillator Configuration ...................................................... 17 EC .............................................................................. 17 ECIO .......................................................................... 17 HS .............................................................................. 17 HS + PLL ................................................................... 17 LP .............................................................................. 17 RC .............................................................................. 17 RCIO .......................................................................... 17 XT .............................................................................. 17 Oscillator Selection .......................................................... 195 Oscillator, Timer1 ..............................................107, 109, 115 Oscillator, Timer3 ............................................................. 113 Oscillator, WDT ................................................................ 203 |
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