18F452 datasheet(326/332 Pages) MICROCHIP

326 / 332 page

PIC18FXX2

DS39564B-page 324

 2002 Microchip Technology Inc.

Example SPI Master Mode (CKE = 0) ..................... 278

Example SPI Master Mode (CKE = 1) ..................... 279

Example SPI Slave Mode (CKE = 0) ....................... 280

Example SPI Slave Mode (CKE = 1) ....................... 281

External Clock (All Modes except PLL) .................... 271

First START Bit Timing ............................................ 153

I2C Bus Data ............................................................ 282

I2C Bus START/STOP Bits ...................................... 282

I2C Master Mode (Reception, 7-bit Address) ........... 157

I2C Master Mode (Transmission,

7 or 10-bit Address) ......................................... 156

I2C Slave Mode Timing (10-bit Reception,

SEN = 0) .......................................................... 142

I2C Slave Mode Timing (10-bit Transmission) ......... 143

I2C Slave Mode Timing (7-bit Reception,

SEN = 0) .......................................................... 140

I2C Slave Mode Timing (7-bit Reception,

SEN = 1) .................................................. 146, 147

I2C Slave Mode Timing (7-bit Transmission) ........... 141

Low Voltage Detect .................................................. 192

Master SSP I2C Bus Data ........................................ 284

Master SSP I2C Bus START/STOP Bits .................. 284

Parallel Slave Port (PIC18F4X2) .............................. 277

Parallel Slave Port (Read) ........................................ 101

Parallel Slave Port (Write) ........................................ 100

PWM Output ............................................................. 122

Repeat START Condition ......................................... 154

RESET, Watchdog Timer (WDT),

Oscillator Start-up Timer (OST) and

Power-up Timer (PWRT) ................................. 273

Slave Synchronization .............................................. 131

Slaver Mode General Call Address Sequence

(7 or 10-bit Address Mode) .............................. 148

Slow Rise Time (MCLR Tied to VDD) ......................... 33

SPI Mode (Master Mode) ......................................... 130

SPI Mode (Slave Mode with CKE = 0) ..................... 132

SPI Mode (Slave Mode with CKE = 1) ..................... 132

Stop Condition Receive or Transmit Mode .............. 158

Time-out Sequence on POR w/PLL Enabled

(MCLR Tied to VDD) ........................................... 33

Time-out Sequence on Power-up

(MCLR Not Tied to VDD)

Case 1 ................................................................ 32

Case 2 ................................................................ 32

Time-out Sequence on Power-up

(MCLR Tied to VDD) ........................................... 32

Timer0 and Timer1 External Clock ........................... 275

Timing for Transition Between Timer1 and

OSC1 (HS with PLL) .......................................... 23

Transition Between Timer1 and OSC1

(HS, XT, LP) ....................................................... 22

Transition Between Timer1 and OSC1

(RC, EC) ............................................................ 23

Transition from OSC1 to Timer1 Oscillator ................ 22

USART Asynchronous Master Transmission ........... 173

USART Asynchronous Master Transmission

(Back to Back) .................................................. 173

USART Asynchronous Reception ............................ 175

USART Synchronous Receive (Master/Slave) ......... 286

USART Synchronous Reception

(Master Mode, SREN) ...................................... 178

USART Synchronous Transmission ......................... 177

USART Synchronous Transmission

(Master/Slave) .................................................. 286

USART Synchronous Transmission

(Through TXEN) .............................................. 177

Wake-up from SLEEP via Interrupt .......................... 206

Timing Diagrams Requirements

Master SSP I2C Bus START/STOP Bits .................. 284

Timing Requirements

A/D Conversion ........................................................ 288

Capture/Compare/PWM (CCP1 and CCP2) ............ 276

CLKO and I/O .......................................................... 273

Example SPI Mode (Master Mode, CKE = 0) .......... 278

Example SPI Mode (Master Mode, CKE = 1) .......... 279

Example SPI Mode (Slave Mode, CKE = 0) ............ 280

Example SPI Slave Mode (CKE = 1) ....................... 281

External Clock .......................................................... 271

I2C Bus Data (Slave Mode) ..................................... 283

Master SSP I2C Bus Data ........................................ 285

Parallel Slave Port (PIC18F4X2) ............................. 277

RESET, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer and

Brown-out Reset Requirements ....................... 274

Timer0 and Timer1 External Clock .......................... 275

USART Synchronous Receive ................................. 286

USART Synchronous Transmission ........................ 286

Timing Specifications

PLL Clock ................................................................ 272

TRISE Register

PSPMODE Bit .....................................................95, 100

TSTFSZ ........................................................................... 251

Two-Word Instructions

Example Cases .......................................................... 41

TXSTA Register

BRGH Bit ................................................................. 168

Universal Synchronous Asynchronous

Receiver Transmitter. See USART

USART ............................................................................. 165

Asynchronous Mode ................................................ 172

Associated Registers, Receive ........................ 175

Associated Registers, Transmit ....................... 173

Receiver .......................................................... 174

Transmitter ....................................................... 172

Baud Rate Generator (BRG) ................................... 168

Associated Registers ....................................... 168

Baud Rate Error, Calculating ........................... 168

Baud Rate Formula .......................................... 168

Baud Rates for Asynchronous Mode

(BRGH = 0) .............................................. 170

Baud Rates for Asynchronous Mode

(BRGH = 1) .............................................. 171

Baud Rates for Synchronous Mode ................. 169

High Baud Rate Select (BRGH Bit) ................. 168

Sampling .......................................................... 168

Serial Port Enable (SPEN Bit) ................................. 165

Synchronous Master Mode ...................................... 176

Associated Registers, Reception ..................... 178

Associated Registers, Transmit ....................... 176

Reception ........................................................ 178

Transmission ................................................... 176

Synchronous Slave Mode ........................................ 179

Associated Registers, Receive ........................ 180

Associated Registers, Transmit ....................... 179

Reception ........................................................ 180

Transmission ................................................... 179

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