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ADF4355-2 Datasheet(PDF) 34 Page - Analog Devices

Part # ADF4355-2
Description  Programmable output power level
PDF  38 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4355-2 Datasheet(HTML) 34 Page - Analog Devices

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Data Sheet
ADF4355-2
Rev. B | Page 33 of 37
PLL Low-Pass Filter Settling Time
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is also modeled
in the ADIsimPLL design tool.
The total lock time for changing frequencies is the sum of the
four separate times (synthesizer lock, VCO band selection, ALC
timeout, and PLL settling time) and is all modeled in the
ADIsimPLL design tool.



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