Data Sheet

ADF4355-2

Rev. B | Page 19 of 37

N16

N15

...

N5

N4

N3

N2

N1

INTEGER VALUE (INT)

00

...

00000

NOT ALLOWED

00

...

00001

NOT ALLOWED

00

...

00010

NOT ALLOWED

..

...

....

.

...

00

...

10110

NOT ALLOWED

00

...

10111

23

00

...

11000

24

..

...

....

.

...

11

...

11101

65533

11

...

11110

65534

11

...

11111

65535

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

DB0

N16

N15N14N13N12

N11N10

N9

RESERVED

16-BIT INTEGER VALUE (INT)

CONTROL

BITS

N8

N7

N6

N5

N4

N3

N2

N1

C4(0) C3(0) C2(0)

INTMIN = 75 WITH PRESCALER = 8/9

PR1

PRESCALER

04/5

18/9

PR1

AC1

0

0

0

0

0

0

0

0

0

0

C1(0)

DB31

AC1

VCO

AUTOCAL

0DISABLED

1

ENABLED

Figure 30. Register 0

REGISTER 0

Control Bits

With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 30

shows the input data format for programming this register.

Reserved

Bits[DB31:DB22] are reserved and must be set to 0.

Automatic Calibration (Autocalibration)

Write to Register 0 to enact (by default) the VCO autocalibration,

and to choose the appropriate VCO and VCO subband. Write 1

to the AC1 bit (Bit DB21) to enable the autocalibration, which is

the recommended mode of operation.

Set the AC1 bit to 0 to disable the autocalibration, which leaves

the ADF4355-2 in the same band it was already in when

Register 0 is updated.

Disable the autocalibration only for fixed frequency applications,

phase adjust applications, or very small (<10 kHz) frequency

jumps. Toggling autocalibration is also required when changing

frequency (see the Frequency Update Sequence section for

additional details).

Prescaler Value

The dual modulus prescaler (P/P + 1), along with the INT,

FRACx, and MODx counters, determines the overall division

ratio from the VCO output to the PFD input. The PR1 bit

(Bit DB20) in Register 0 sets the prescaler value.

Operating at CML levels, the prescaler takes the clock from the

VCO output and divides it down for the counters. It is based on

a synchronous 4/5 core. When the prescaler is set to 4/5, the

maximum RF frequency allowed is 7 GHz. The prescaler limits

16-Bit Integer Value

The 16 INT bits (Bits[DB19:DB4]) set the INT value, which

determines the integer part of the feedback division factor. The

INT value is used in Equation 3 (see the INT, FRAC, MOD, and

R Counter Relationship section). All integer values from 23 to

32,767 are allowed for the 4/5 prescaler. For the 8/9 prescaler, the

minimum integer value is 75, and the maximum value is 65,535.