HMC832 datasheet(4/49 Pages) AD

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Data Sheet

HMC832

SPECIFICATIONS

VPPCP, VDDLS, VCC1, VCC2 = 3.3 V; RVDD, AVDD, DVDD, VCCPD, VCCHF, VCCPS = 3.3 V minimum and maximum specified

across the temperature range of −40°C to +85°C.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RF OUTPUT CHARACTERISTICS

Output Frequency

3000

MHz

VCO Frequency at PLL Input

1500

3000

MHz

RF Output Frequency at fVCO

1500

3000

MHz

OUTPUT POWER

RF Output Power at Fundmental

Frequency

2000 MHz across all frequencies (see Figure 25)

Maximum gain setting: VCO_REG 0x07[3:0] = 11d

single-ended

dBm

Gain Setting 6: VCO_REG 0x07[3:0] = 6d differential

dBm

Output Power Control Range

1 dB steps

HARMONICS FOR FUNDAMENTAL

MODE

fo Mode at 2 GHz

2nd/3rd/4th

−20/−29/−45

dBc

fo/2 Mode at 2 GHz/2 = 1 GHz

2nd/3rd/4th

−26/−10/−34

dBc

fo/30 Mode at 3 GHz/30 = 100 MHz

2nd/3rd/4th

−33/−10/−40

dBc

fo/62 Mode at 1550 MHz/62 = 25 MHz

2nd/3rd/4th

−40/−6/−43

dBc

VCO OUTPUT DIVIDER

VCO RF Divider Range

1, 2, 4, 6, 8, … 62

PLL RF DIVIDER CHARACTERISTICS

19-Bit N-Divider Range (Integer)

Maximum = 219 − 1

524,287

19-Bit N-Divider Range (Fractional)

Fractional nominal divide ratio varies (±4) dynamically

maximum

524,283

REFERENCE (XREFP PIN) INPUT

CHARACTERISTICS

Maximum

XREFP Input Frequency

350

MHz

XREFP Input Level

AC-coupled1

−6

+12

dBm

XREFP Input Capacitance

14-Bit R-Divider Range

16,383

PHASE DETECTOR (PD)2

PD Frequency Fractional Mode3

100

MHz

PD Frequency Integer Mode

100

MHz

CHARGE PUMP

Output Current

0.02

2.54

Charge Pump Gain Step Size

µA

PD/Charge Pump SSB Phase Noise

50 MHz reference, input referred

1 kHz

−143

dBc/Hz

10 kHz

Add 2 dB for fractional mode

−150

dBc/Hz

100 kHz

Add 3 dB for fractional mode

−152

dBc/Hz

LOGIC INPUTS

VSW

% DVDD

LOGIC OUTPUTS

Output High Voltage (VOH )

DVDD

Output Low Voltage (VOL )

Output Impedance

100

200

Maximum Load Current

1.5

POWER SUPPLY VOLTAGES

3.3 V Supplies

AVDD, VCCHF, VCCPS, VCCPD, RVDD, DVDD, VPPCP,

VDDLS, VCC1, VCC2

3.1

3.3

3.5

Rev. A | Page 3 of 48

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