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AM5706 Datasheet(PDF) 5 Page - Texas Instruments |
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AM5706 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 387 page  5 AM5706, AM5708 www.ti.com SPRS961A – AUGUST 2016 – REVISED FEBRUARY 2017 Submit Documentation Feedback Product Folder Links: AM5706 AM5708 Revision History Copyright © 2016–2017, Texas Instruments Incorporated 2 Revision History Changes from August 16, 2016 to February 28, 2017 (from * Revision (August 2016) to A Revision) Page • Updated DDR3 max speed in Section 1.1 ......................................................................................... 1 • Updated features list ................................................................................................................. 1 • Added PCIe_SS2 support in Section 1.1 .......................................................................................... 1 • Updated Block Diagram .............................................................................................................. 3 • Added device hex codes to Table 3-1 ............................................................................................. 6 • Added PCIe_SS2 support Table 3-1 ............................................................................................... 7 • Added ”Related Products” section. Updated TRM/Errata documentation name resources in Section 8.3 ............... 8 • Updated column description parameter [4] in Ball Characteristics Table .................................................... 10 • Updated chapter with template alignment and content enhancement ....................................................... 11 • Updated DSIS Description for "blank" in Section 4.2 ........................................................................... 11 • Update VIP IOSETs and ball numbers in Section 4.3.1 ........................................................................ 66 • Added missing ball numbers for alternative signals to the corresponding signal description tables ..................... 68 • Added PCIe_SS2 support in Table 4-16 ......................................................................................... 81 • Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 4-27 ........................................ 98 • Fixed typos and clean-up in Section 5.4 ....................................................................................... 119 • Updated DDR3 max speed in Section 5.5 ...................................................................................... 122 • Updated boot voltages for VD_DSP in Table 5-4 ............................................................................. 122 • Added PCIe_SS2 support in Table 5-6 ......................................................................................... 123 • Updated IQ1833 Buffers DC Electrical Characteristics Table ............................................................... 144 • Updated rstoutn timing in figure Power-Up Sequencing to start after Note 9 .............................................. 153 • Updated power up and down sequencing to allow either non-RTC or RTC PMIC implementations ................... 153 • Updated chapter with template alignment and content enhancement ...................................................... 156 • Added DSS_VIRTUAL1 and MMC2_VIRTUAL2 options to the Timing Chapter Section 5.9.6 ......................... 166 • Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 5-28 ...................................... 166 • Updated VIN Data Manual Timing Mode descriptions in Table 5-28 ....................................................... 166 • Updated Timing specification values for VIP, DSS VOUT, GPMC, McSPI, QSPI, McASP, Ethernet and MMC1-4 Interfaces ........................................................................................................................... 168 • Fixed missing ball for vin1a_d15 in Vin1 IOSET9 ............................................................................. 169 • Update VIP IOSETs and ball numbers in Table 5-30 ......................................................................... 169 • Added missing balls for vin1b in IOSET7 in Table 5-30 ...................................................................... 169 • Updated Manual Modes for VIP, DSS, MMC and PRU-ICSS Interfaces ................................................... 174 • Added DSS clock jitter footnotes on Table 5-38 and Table 5-39 ............................................................ 180 • Removed DPI2 (xref_clk2 clock reference) IOSET2 from Timing tables .................................................. 180 • Updated are Virtual Mode Case Details for McASP2 when AXR(Inputs)/CLKX/FSX in 80MHz and non-80MHz operation. .......................................................................................................................... 236 • Fixed typo in naming of figures McASP1-8 for SYNC Mode in Table 5-82 ................................................ 244 • Removed McASP "ahclkx" signals from Table 5-82 and Table 5-83 ....................................................... 245 • Added PCIe_SS2 support in Section 5.9.6.17 ................................................................................. 249 • Updated ball number for RMII_MHZ_50_CLK in Table 5-99 ................................................................ 257 • Removed PRU1 mii IOSET4 from Table 5-174 ................................................................................ 298 • Removed 1149.7 (cJTAG) support .............................................................................................. 314 • Updated Block Diagram in Section 6.2 ......................................................................................... 317 • Updated chapter with template alignment and content enhancement ...................................................... 332 • Added PCIe_SS2 support in Section 6.10.10 .................................................................................. 340 • Added content for Section 7.1 Power Supply Mapping ....................................................................... 352 • Updated DDR3 max speed in Section 7.2.2.5 ................................................................................. 357 • Updated broken note in High-Speed Bypass Capacitors Table ............................................................. 360 • Updated PDN application report link and literature number in Section 7.4 ............................................... 376 • Updated symbolization in Printed Device Reference Figure 8-1 and Nomenclature Description Table 8-1 ........... 380 |
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