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DAC38RF82 Datasheet(PDF) 49 Page - Texas Instruments |
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DAC38RF82 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 139 page  49 DAC38RF82, DAC38RF89 www.ti.com SLASEA6 – FEBRUARY 2017 Product Folder Links: DAC38RF82 DAC38RF89 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 8.3.18.3 JESD and Interpolation Programming Table 38 lists the register field values required for each JESD and interpolation mode. The register field addresses are listed in Table 39. Table 38. Register Programming for JESD and Interpolation Mode Mode Register Field Programming L-M-F-S-Hd 1 TX/2TX Interp CLKJESD_DIV INTERP (4-0) CLKJESD _DIV (3-0) CLKJESD _OUT_DI V (3-0) L_M1 (4-0) F_M1 (7-0) M_M1 (7-0) S_M1 (4-0) HD N_M1/N’_ M1 (4-0) 82121/NA 6 div24 00011 0110 0011 00111 0x00 0x01 00001 1 01111 8 div32 00100 0111 0100 12 div48 00110 1010 0110 16 div64 01000 1011 0111 42111/84111 6 div12 00011 0010 0011 00011 0x00 0x01 00000 1 01111 8 div16 00100 0011 0100 10 div20 00101 0101 0101 12 div24 00110 0110 0110 16 div32 01000 0111 0111 18 div36 01001 1001 1000 24 div48 01100 1010 1010 22210/44210 8 div8 00100 0001 0100 00001 0x01 0x01 00000 0 01111 12 div12 00110 0010 0110 16 div16 01000 0011 0111 18 div18 01001 0100 1000 20 div20 01010 0101 1001 24 div24 01100 0110 1010 12410/24410 16 div8 01000 0001 0111 00000 0x03 0x01 00000 0 01111 24 div12 01100 0010 1010 44210/88210 8 div8 00100 0001 0100 00011 0x01 0x03 00000 0 01111 12 div12 00110 0010 0110 16 div16 01000 0011 0111 24 div24 01100 0110 1010 24410/48410 16 div8 01000 0001 0111 00011 0x03 0x03 00000 0 01111 24 div12 01100 0010 1010 81180/NA 1 div16 00000 0011 0001 00111 0x00 0x00 00111 0 00111 41380/82380 1 div5.333 00000 1100 0000 00011 0x02 0x01 00111 0 01011 2 div10.667 00001 11001 0001 41121/ 82121 1 div4 00100 0001 0100 00001 0x01 0x01 00000 0 01111 2 div8 00110 0010 0110 4 div16 01000 0011 0111 24310/48310 24 div16 01100 0011 1010 00011 0x02 0x03 00000 0 01011 Table 39. Register Field Addresses for JESD and Interpolation Programming Register Field Name Register Register Address Bit(s) Hyperlink INTERP MULTIDUC_CFG1 0x0A 12-8 8.5.13 CLKJESD_DIV SERDES_CLK 0x25 15-12 8.5.28 CLKJESD_OUT_DIV 11-8 L_M1 JESD_K_L 0x4C 4-0 8.5.47 F_M1 JESD_RBD_F 0x4B 7-0 8.5.46 M_M1 JESD_M_S 0x4D 15-8 8.5.48 S_M1 4-0 |
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