SC16C2552 datasheet(21/38 Pages) PHILIPS

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Philips Semiconductors

SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Product data

Rev. 03 — 20 June 2003

21 of 38

9397 750 11636

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the

modem, or other peripheral device to which the SC16C2552 is connected. Four bits

of this register are used to indicate the changed information. These bits are set to a

logic 1 whenever a control input from the modem changes state. These bits are set to

a logic 0 whenever the CPU reads this register.

[1]

Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.

LSR[0]

Receive data ready.

Logic 0 = No data in receive holding register or FIFO (normal default

condition).

Logic 1 = Data has been received and is saved in the receive holding

Table 17:

Line Status Register bits description…continued

Bit

Symbol

Description

Table 18:

Modem Status Register bits description

Bit

Symbol

Description

MSR[7]

Carrier Detect, CD. During normal operation, this bit is the complement

of the CD input. Reading this bit in the loop-back mode produces the

state of MCR[3] (OPA/OPB).

MSR[6]

Ring Indicator, RI. During normal operation, this bit is the complement of

the RI input. Reading this bit in the loop-back mode produces the state of

MCR[2] (OP1).

MSR[5]

Data Set Ready, DSR. During normal operation, this bit is the

complement of the DSR input. During the loop-back mode, this bit is

equivalent to MCR[0] (DTR).

MSR[4]

Clear To Send, CTS. During normal operation, this bit is the complement

of the CTS input. During the loop-back mode, this bit is equivalent to

MCR[1] (RTS).

MSR[3]

∆CD [1]

Logic 0 = No CD change (normal default condition).

Logic1=The CD input to the SC16C2552 has changed state since

the last time it was read. A modem Status Interrupt will be generated.

MSR[2]

∆RI [1]

Logic 0 = No RI change (normal default condition).

Logic1=The RI input to the SC16C2552 has changed from a logic 0

to a logic 1. A modem Status Interrupt will be generated.

MSR[1]

∆DSR [1]

Logic 0 = No DSR change (normal default condition).

Logic1=The DSR input to the SC16C2552 has changed state since

the last time it was read. A modem Status Interrupt will be generated.

MSR[0]

∆CTS [1]

Logic 0 = No CTS change (normal default condition).

Logic1=The CTS input to the

SC16C2552 has changed state since

the last time it was read. A modem Status Interrupt will be generated.

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