SC16C2552 datasheet(3/38 Pages) PHILIPS

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Philips Semiconductors

SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Product data

Rev. 03 — 20 June 2003

3 of 38

9397 750 11636

Pinning information

5.1 Pinning

5.2 Pin description

Fig 2.

PLCC44 pin conﬁguration.

SC16C2552IA44

002aaa124

XTAL1

GND

XTAL2

CHSEL

INTB

RXA

TXA

DTRA

RTSA

MFA

INTA

Vcc

TXRDYB

RIB

CDB

DSRB

Table 2:

Pin description

Symbol

Type

Description

A2-A0

10, 14,

CHSEL

Channel Select. UART channel A or B is selected by the logical state of this pin when

the CS is a logic 0. A logic 0 on CHSEL selects the UART channel ‘B’, while a logic 1

selects UART channel ‘A’.

Chip Select (Active-LOW). This function is selects channel ‘A’ or ‘B’, in accordance

with the logical state of the CHSEL pin. This allows data to be transferred between the

user CPU and the SC16C2552, or the SC16C2552 and the CPU for a channel selected

by CHSEL. MF[0] overrides CHSEL while in the write cycle mode, allowing the user to

write both channel registers simultaneously with one write cycle.

D0-D7

2-9

I/O

Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for transferring

information to or from the controlling CPU. D0 is the least signiﬁcant bit and the ﬁrst

data bit in a transmit or receive serial data stream.

GND

12, 22

Signal and power ground.

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