MB9B100 Series

[LIN]

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LIN protocol Rev.2.1 supported

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Full-duplex double buffer

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Master/Slave mode supported

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LIN break field generate (can be changed 13-16bit length)

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LIN break delimiter generate (can be changed 1-4bit length)

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Various error detect functions available (parity errors, framing errors, and overrun errors)

[I

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Standard mode (Max.100kbps) / High-speed mode (Max.400Kbps) supported



DMA Controller (8channels)

DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.

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8 independently configured and operated channels

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Transfer can be started by software or request from the built-in peripherals

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Transfer address area: 32bit(4Gbyte)

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Transfer mode: Block transfer/Burst transfer/Demand transfer

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Transfer data type: byte/half-word/word

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Transfer block count: 1 to 16

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Number of transfers: 1 to 65536

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A/D Converter (Max. 16channels)

[12-bit A/D Converter]

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Successive Approximation Register type

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Built-in 3unit

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Conversion time: 1.0μs@5V

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Priority conversion available (priority at 2levels)

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Scanning conversion mode

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Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:

4steps)

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Base Timer (Max. 8channels)

Operation mode is selectable from the followings for each channel.

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16-bit PWM timer

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16-bit PPG timer

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16/32-bit reload timer

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16/32-bit PWC timer

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General Purpose I/O Port

MB9B100 series can use its pins as I/O ports when they are not used for external bus or peripherals.

Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be

allocated.

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Capable of pull-up control per pin

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Capable of reading pin level directly

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Built-in the port relocate function

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Up to 100 fast I/O Ports@120pin Package

3

FUJITSU SEMICONDUCTOR CONFIDENTIAL

r2.1

DS706-00007-1v0-E