WTS701MFSLASHT datasheet(22/77 Pages) WINBOND

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WTS701

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Table 4. Status Bit Description.

Byte

Bit Name

Bit #

RDY

Ready to accept commands. After the device has been powered up,

this bit is set after the Power Up latency delay.

CNVT

Converting. This bit is set anytime while the conversion process is

running. If this bit is clear when a convert command is sent, the count in

the Count register is set to 0.

BEMP

The text input buffer is empty. This bit is set anytime the input buffer is

empty.

BFUL

The text input buffer is full. This bit is cleared after 128 bytes become

available in the input buffer.

COD

CODEC is enabled. This is set when the CODEC has been enabled by

the SCOD command.

ICNV

Conversion finished interrupt has occurred. To stop CODEC

transmission or Power Down the analog outputs an IDLE command

should be sent. This bit is cleared by RINT command.

IBUF

The input text buffer been filled above the defined threshold and then

gone below the defined threshold. The buffer threshold level is set by

the SCOM command. If set by the SCOM command, the INT pin will

also go LOW. This bit is cleared by RINT command.

ICNT

Count interrupt has occurred. This interrupt is generated every time a

word has been spoken if activated by the SCOM command. This bit is

cleared by RINT command.

ICMD

Command was ignored. Anytime ICMD is set, the transaction must

revert to a single word command and the command must be resent.

Any data sent will be ignored.

IABB

Abbreviation interrupt has occurred, abbreviation add or abbreviation

delete has been completed. Now the ENTER_RRSM command can be

sent.

R/ B

Current state of the R/ B pin. If this bit is 0, any data sent will be

ignored.

*5 bits are reserved.

7.3.3 Interrupt Handler

If an interrupt has occurred, no further interrupts will be registered until the first interrupt has been

cleared. Only one interrupt can be active at any time.

The RINT command will read and clear pending interrupts while the RDST command will read

interrupts without clearing them.

Make sure that all interrupts that are not being used are masked by clearing the corresponding bits in

the COM register.

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