ADV7312KST datasheet(15/84 Pages) AD

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ADV7312

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PIN FUNCTION DESCRIPTIONS

Mnemonic

Input/Output

Function

DGND

Digital Ground.

AGND

Analog Ground.

CLKIN_A

Pixel Clock Input for HD Only (74.25 MHz), PS Only (27 MHz), SD Only (27 MHz).

CLKIN_B

Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz

(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.

COMP1,2

Compensation Pin for DACs. Connect 0.1

µF capacitor from COMP pin to V

AA.

DAC A

CVBS/Green/Y/Y Analog Output.

DAC B

Chroma/Blue/U/Pb Analog Output.

DAC C

Luma/Red/V/Pr Analog Output.

DAC D

In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Y/Green [HD] Analog Output.

DAC E

In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Pr/Red Analog Output.

DAC F

In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD

Mode: Pb/Blue [HD] Analog Output.

P_HSYNC

Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

P_VSYNC

IVideo Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

P_BLANK

IVideo Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

S_BLANK

I/O

Video Blanking Control Signal for SD Only.

S_HSYNC

I/O

Video Horizontal Sync Control Signal for SD Only.

S_VSYNC

I/O

Video Vertical Sync Control Signal for SD Only.

Y7–Y0

SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan

data. The LSB is set up on Pin Y0.

C7–C0

Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data.

The LSB is set up on Pin C0.

S7–S0

SD or Progressive Scan/HDTV Input Port for Cr[Red/V] data in 4:4:4 input mode. LSB is set up

on Pin S0.

RESET

This input resets the on-chip timing generator and sets the ADV7312 into default register setting.

RESET is an active low signal.

RSET1,2

IA 3040

Ω resistor must be connected from this pin to AGND and is used to control the amplitudes

of the DAC outputs.

SCLK

2C Port Serial Interface Clock Input.

SDA

I/O

2C Port Serial Data Input/Output.

ALSB

TTL Address Input. This signal sets up the LSB of the I

2C address. When this pin is tied low,

the I

2C filter is activated, which reduces noise on the I2C interface.

VDD_IO

PPower Supply for Digital Inputs and Outputs.

VDD

PDigital Power Supply.

VAA

PAnalog Power Supply.

VREF

I/O

Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

EXT_LF

External Loop Filter for the Internal PLL.

RTC_SCR_TR I

Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input.

2CI

This input pin must be tied high (VDD_IO) for the ADV7312 to interface over the I

2C port.

GND_IO

Digital Input/Output Ground.

ADV7312KST Datasheet(PDF) 15 Page - Analog Devices

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