Q1

MTB1306

D2 PAK

TP5

TP6

TP7

TP8

TP9

TP10

5 V_Input

GND_Input

12 V_Input

V_Logic

V_5P0_STBV

-12 V_Input

R1

10

C12

0.1

mF

VTT (+1.25V, 2A)

VREF (+1.25V, 2mA)

VDDQ (+2.5V, 8A)

Q2

MTB1306

D2 PAK

NCP1571

SO-8

L1

1

mH

Q5

MTD20P03HDL

DPAK

C16

C17

VCC

GATE(H)

8

7

6

5

1

2

3

4

C1

1800

mF

10V

C2

1800

mF

10V

C4

0.1

mF

C5

1800

mF

10V

Prov.

C7

1800

mF

6.3V

Prov.

C8

1800

mF

6.3V

C9

0.1

mF

C11

1800

mF

6.3V

D1

MBRM110LT

PowerMite Prov.

C15

1

mF

OUT

OUT

Q4

NTD4302

D2 PAK

TP1

TP2

TP3

TP4

Tol. = 1.0%

Tol. = 1.0%

U2A

LM358

Micro8

ON OFF

VOUT

C24

1

mF

C20

1800

mF

6.3V

Prov.

R7

1k

R5

10K

C21

1800

mF

6.3V

Prov.

R6

10K

C22

0.1

mF

C23

1800

mF

6.3V

C18

0.15

mF

R9

100

R8

200

C19

1.25V_Ref

GND_Output

1.25V_Vtt

6

5

7

R3

20k

R4

13k

L2

2.2

mH

Tol = 1.0%

To = 1.0%

Q3

MTB1306

D2PAK

C6

100pF

2.5V

0.1

mF

0.1

mF

2

3

4

V-

V+

8

R2

47k

C13

0.01

mF

C14

0.1

mF

MC33375ST-2.5T3

SOT-223

1

2

3

4

U2B

LM358

C3

1800

mF

10V

GATE(L)

Vfb

GND

PWRGD

PGDELAY

COMP

C10

1800

mF

6.3V

GND

VIN

Figure 2. DDR Memory Reference Design

2

mF

Note: The provisional components were not used in the verification of the reference design.

U1

U3 Prov.

−

−

1