AND8090 datasheet(5/20 Pages) ONSEMI

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AND8090/D

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SIGNAL LEVELS

AC HIGH and LOW Levels − The HIGH level referred

to in this application note corresponds to the IEEE “topline,”

and the LOW level corresponds to the IEEE “baseline” as

shown in Figure 5. The 50% point lies halfway between the

HIGH and LOW levels. Refer to IEEE Standard 194−1977

for further voltage level information.

Figure 5. HIGH and LOW Waveform Definition

HIGH

LOW

50%

(topline)

(baseline)

VIH/VOH

VIL/VOL

Input Levels − Operational differential input levels are

specified by VPP and the VIHCMR range as described in the

“Differential

Characteristics”

section.

Operational

single−ended input levels are specified by VIL and VIH as

described in the “Single−Ended Characteristics” section.

Output Levels − Output signals may be differential or

single−ended. AC characteristics for ON Semiconductor

devices with ECL outputs are typically measured for an

output termination of 50

W to V

TT (the termination voltage

equal to VCC − 2.0 V). HIGH and LOW output levels range

between the boundary and threshold values for the

respective HIGH and LOW input levels specified on data

sheets. Output logic levels are shown in Figure 6.

VOHmax

HIGH

VOHmin

VOLmax

LOW

VOLmin

Boundary

Threshold

Boundary

Figure 6. Output Logic Levels

Oscilloscope Averaging − Digital sampling oscilloscopes

use an algorithm to determine the average level over a pulse

width to establish the HIGH and LOW levels. An example is

shown in Figure 7. The horizontal cursors at the HIGH and

LOW levels indicate the determined average levels.

Figure 7. HIGH and LOW Waveform Levels

HIGH

LOW

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