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AND8090D Datasheet(PDF) 12 Page - ON Semiconductor |
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AND8090D Datasheet(HTML) 12 Page - ON Semiconductor |
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12 / 20 page ![]() AND8090/D http://onsemi.com 12 For differential inputs, it is measured between the crosspoints of the rise and fall transitions as shown in Figure 31. Figure 31. Differential Input Pulse Width tPW VIH VIL Xpt Xpt Setup and Hold Time Applicability – Only synchronous clocked devices have setup (tS or tSETUP) and hold (tH or tHOLD) times. Timing Window – The minimum setup requirement and the minimum hold requirement specify the timing window where the input must not change in order to successfully clock the input. The setup time specifies the left edge of the timing window, and the hold time specifies the right edge of the window. Both timing requirements must be met in order to successfully clock the input. Measurement Points – Differential crosspoints (refer to the “Differential Characteristics” section) and single−end 50% points (refer to the “Single−Ended Characteristics” section) are used as time measurement points. Note from the following figures that the 50% point of the active clock edge is the time origin of all setup and hold time measurements. Minimum Setup Time – The following is true of minimum setup times. • Minimum setup times are usually positive, and they specify the minimum length of time that the input must remain unchanged before the active clock edge in order to successfully clock the input. Positive setup times therefore indicate that the left edge of the timing window is before the active clock edge. • Negative minimum setup times specify the minimum length of time that the input must remain unchanged after the active clock edge in order to successfully clock the input. Negative setup times therefore indicate that the left edge of the timing window is after the active clock edge. Minimum Hold Time – The following is true of minimum setup times. • Minimum hold times are usually positive, and they specify the minimum length of time that the input must remain unchanged after the active clock edge in order to successfully clock the input. Positive hold times therefore indicate that the right edge of the timing window is after the active clock edge. • Negative hold times specify the minimum length of time that the input must remain unchanged before the active clock edge in order to successfully clock the input. Negative hold times therefore indicate that the right edge of the timing window is before the active clock edge. Typical Setup and Hold Times – The typical setup and hold times specified on data sheets are not guaranteed, and they are only included for failure analysis calculations. They are measured by independently moving the left and right edges of the timing window about the active clock edge until the outputs no longer function properly. Positive Setup and Positive Hold Example – The MC100EP29 data sheet specifies the following: • The minimum setup time of positive 100 ps indicates that the left edge of the timing window is 100 ps before the active rising clock edge. • The minimum hold time of positive 100 ps specifies that the right edge of the timing window is 100 ps after the active rising clock edge. The setup time requirement and the hold time requirement were both met in the example shown in Figure 32, therefore the LOW−to−HIGH output transition occurs after the CLK rising edge propagation delay of 420 ps. Note that the input cannot change within the timing window of 200 ps. Only one side of the differential clocks, inputs, and outputs are shown in Figure 32. Figure 32. Positive Setup and Positive Hold Example t(ps) CLK 50% 50% 50% INPUT OUTPUT tPHL 420 ps +100 ts(min) +100 th(min) |
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