AND8090D datasheet(14/20 Pages) ONSEMI

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AND8090/D

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Negative Setup and Negative Hold Comment – The left

edge of the timing window is the setup edge, and the right

edge of the window is the hold edge. A negative setup time

with a negative hold time cannot occur as this principle

would be violated (i.e., the hold edge would occur before the

set edge).

Set and Reset Recovery Time

Applicability – Only devices with a Set input have set

recovery times (tSR), and only devices with a Reset input

have reset recovery times (tRR).

Measurement Points – Differential crosspoints (refer to

the “Differential Characteristics” section) and single−end

50% points (refer to the “Single−Ended Characteristics”

section) are used as time measurement points. Note from the

following figures that the 50% point of the active clock edge

is the time origin of all set and reset recovery time

measurements.

Minimum Set Recovery Time – This parameter defines

the minimum length of time that Set has to be inactive before

an active clock edge in order for the output to enter the

non−Set state. In the non−Set state, the output is no longer

dependent upon the Set state.

In the MC100EP29 example shown in Figure 35, the

minimum set recovery time of 150 ps specifies that the

system must be designed so that Set transitions from the

active HIGH state to the inactive LOW state at least 150 ps

before the active rising clock edge. The set recovery timing

requirement (150 ps) and the input setup time requirement

(100 ps) were both met in the example shown in Figure 35,

therefore the output transitions from the Set state (HIGH) to

the input state (LOW). The transition takes place after the

specified 420 ps HIGH−to−LOW CLK propagation delay.

Minimum Reset Recovery Time – This parameter

defines the minimum length of time that Reset has to be

inactive before an active clock edge in order for the output

to enter the non−Reset state. In the non−Reset state, the

output is no longer dependent upon the Reset state.

In the MC100EP29 example shown in Figure 36, the

minimum reset recovery time of 150 ps specifies that the

system must be designed so that Reset transitions from the

active HIGH state to the inactive LOW state at least 150 ps

before the active rising clock edge. The reset recovery

timing requirement (150 ps) and the input setup time

requirement (100 ps) were both met in the example shown

in Figure 36, therefore the output transitions from the Set

state (HIGH) to the input state (LOW). The transition takes

place after the specified 420 ps HIGH−to−LOW CLK

propagation delay.

Figure 35. Set Recovery Time Example

tSR(ps)

CLK

50%

INPUT

OUTPUT

150

tSR(min)

tPHL

420 ps

SET

100

ts(min)

ts(ps)

50%

Figure 36. Reset Recovery Time Example

tRR(ps)

CLK

50%

INPUT

OUTPUT

150

tRR(min)

tPLH

420 ps

RESET

100

ts(min)

50%

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