LMV981 datasheet(13/18 Pages) NSC

13 / 18 page

Application Note

1.0 INPUT AND OUTPUT STAGE

The rail-to-rail input stage of this family provides more flex-

ibility for the designer. The LMV981/LMV982 use a compli-

mentary PNP and NPN input stage in which the PNP stage

senses common mode voltage near V

− and the NPN stage

senses common mode voltage near V

+. The transition from

the PNP stage to NPN stage occurs 1V below V

+. Since both

input stages have their own offset voltage, the offset of the

amplifier becomes a function of the input common mode

voltage and has a crossover point at 1V below V

This V

OS crossover point can create problems for both DC

and AC coupled signals if proper care is not taken. Large

input signals that include the V

OS crossover point will cause

distortion in the output signal. One way to avoid such distor-

tion is to keep the signal away from the crossover. For

example, in a unity gain buffer configuration and with V

S =

5V, a 5V peak-to-peak signal will contain input-crossover

distortion while a 3V peak-to-peak signal centered at 1.5V

will not contain input-crossover distortion as it avoids the

crossover point. Another way to avoid large signal distortion

is to use a gain of −1 circuit which avoids any voltage

excursions at the input terminals of the amplifier. In that

circuit, the common mode DC voltage can be set at a level

away from the V

OS cross-over point. For small signals, this

transition in V

OS shows up as a VCM dependent spurious

signal in series with the input signal and can effectively

degrade small signal parameters such as gain and common

mode rejection ratio. To resolve this problem, the small

signal should be placed such that it avoids the V

OS cross-

over point. In addition to the rail-to-rail performance, the

output stage can provide enough output current to drive

600

Ω loads. Because of the high current capability, care

should be taken not to exceed the 150˚C maximum junction

temperature specification.

2.0 SHUTDOWN MODE

The LMV981/LMV982 have a shutdown pin. To conserve

battery life in portable applications, the LMV981/LMV982

can be disabled when the shutdown pin voltage is pulled low.

The shutdown pin can’t be left unconnected. In case shut-

down operation is not needed, the shutdown pin should be

connected to V

+ when the LMV981/LMV982 are used. Leav-

ing the shutdown pin floating will result in an undefined

operation mode, either shutdown or active, or even oscillat-

ing between the two modes.

3.0 INPUT BIAS CURRENT CONSIDERATION

The LMV981/LMV982 family has a complementary bipolar

input stage. The typical input bias current (I

B) is 15nA. The

input bias current can develop a significant offset voltage.

This offset is primarily due to I

B flowing through the negative

feedback resistor, R

F. For example, if IB is 50nA and RF is

100k

Ω, then an offset voltage of 5mV will develop (V

OS =IB

F). Using a compensation resistor (RC), as shown in

Figure 1, cancels this effect. But the input offset current (I

OS)

will still contribute to an offset voltage in the same manner.

Typical Applications

4.0 HIGH SIDE CURRENT SENSING

The high side current sensing circuit (Figure 2) is commonly

used in a battery charger to monitor charging current to

prevent over charging. A sense resistor R

SENSE is connected

to the battery directly. This system requires an op amp with

rail-to-rail input. The LMV981/LMV982 are ideal for this ap-

plication because the common mode input range goes up to

the rail.

20021459

FIGURE 1. Canceling the Offset Voltage due to Input

Bias Current

200214H0

FIGURE 2. High Side Current Sensing

LMV981 Datasheet(PDF) 13 Page - National Semiconductor (TI)

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