2.3 N REGISTER

If the address bit is LOW (ADDR=0) when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit

N register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the

control word. Serial data format is shown below in tables 2.3.1 and 2.3.2. The pulse swallow function which determines the divide

ratio is described in section 2.3.3. Data is clocked into the shift register MSB first.

MSB

SHIFT REGISTER BIT LOCATION

LSB

17

16

15

14

13

12

11

10

9

8

7654

3

2

1

0

Register

Data Field

ADDR Field

N

NB_CNTR[9:0]

NA_CNTR[4:0]

CTL_WORD[1:0]

0

N16

N15

N14

N13

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter)

Swallow Count

NA_CNTR[4:0]

(A)

N6

N5

N4

N3

N2

0

00000

1

00001

•

•••••

31

11111

Notes: Swallow Counter Value: 0 to 31

NB_CNTR

≥ NA_CNTR

2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter)

NB_CNTR[10:0]

Divide Ratio

N16

N15

N14

N13

N12

N11

N10

N9

N8

N7

3

0000000

0

1

1

4

0000000

1

0

0

•

•••••••

•

•

•

1023

1111111

1

1

1

Notes: Divide ratio: 3 to 1,023 (Divide ratios less than 3 are prohibited)

NB_CNTR

≥ NA_CNTR

2.3.3 Pulse Swallow Function

The N divider counts such that it divides the VCO RF frequency by (P+1) A times, and then divides by P (B - A) times. The B value

(NB_CNTR) must be

≥ 3. The continuous divider ratio is from 992 to 32,767. Divider ratios less than 992 are achievable as long

as the binary counter value is greater than the swallow counter value (NB_CNTR

≥ NA_CNTR).

f

N=(P x B) + A

f

Output frequency of external voltage controlled oscillator (VCO)

f

Output frequency of the external reference frequency oscillator

R:

Preset divide ratio of binary 10-bit programmable reference counter (2 to 1023)

N:

Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767)

B:

Preset divide ratio of binary 10-bit programmable B counter (3 to 1023)

A:

Preset value of binary 5-bit swallow A counter (0

≤ A ≤ 31, A ≤ B)

P:

Preset modulus of dual modulus prescaler (P=32)

2.3.4 CTL_WORD

MSB

LSB

N1

N0

CNT_RST

PWDN

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