1.9 POWER-DOWN

CE

PD[1:0]

Operating Mode

0

X

Power-down (Asynchronous)

1

0

Normal Operation

1

1

Power-down (Synchronous)

1

2

Counter Reset

1

3

Power-down (Asynchronous)

The LMX2346/7 are power controlled through logical control

of the CE pin in conjunction with programming of the PD

control word. A truth table is provided that describes how the

state of the CE pin and the PD control word set the operating

mode of the device. A complete programming description for

the PD control word is provided in Section 2.3.1.

When the device enters the power-down mode, the oscillator

buffer, RF prescaler, phase detector, and charge pump cir-

cuits are all disabled. The OSC

are all forced to a high impedance state. The reference

divider and feedback divider circuits are disabled and held at

the load point during power-down. When the device is pro-

grammed to normal operation, the oscillator buffer, RF pres-

caler, phase detector, and charge pump circuits are all pow-

ered on. The feedback divider and the reference divider are

held at the load point. This allows the RF Prescaler, feed-

back divider, reference oscillator, and the reference divider

circuitry to reach proper bias levels. After a 1.5 µs delay, the

feedback and reference divider are enabled and they re-

sume counting in “close” alignment (The maximum error is

one prescaler cycle). The MICROWIRE control register re-

mains active and capable of loading and latching in data

while in the power-down mode.

The synchronous power-down function is gated by the

charge pump. When the device is configured for synchro-

nous power-down, the device will enter the power-down

mode upon the completion of the next charge pump pulse

event.

The asynchronous power-down function is NOT gated by the

completion of a charge pump pulse event. When the device

is configured for asynchronous power-down, the part will go

into power down mode immediately.

A counter reset function is provided. When the PD control

word is programmed to Counter Reset, both the feedback

divider and the reference divider are disabled and held at

their load point. When the device is programmed to normal

operation, both the feedback divider and the reference di-

vider are enabled (without a delay) and resume counting in

“close” alignment (The maximum error is one prescaler

cycle).

2.0 Programming Description

2.1 MICROWIRE INTERFACE

The MICROWIRE interface is comprised of an 18-bit shift register, and two control registers. The shift register consists of a 17-bit

DATA field and a 1-bit address (ADDR) field as shown below. When Latch Enable transitions HIGH, data stored in the shift register

is loaded into either the R or N register depending on the state of the ADDR bit. The data is loaded MSB first. The DATA field

assignments for the R and N registers are shown in Section 2.1.1.

MSB

LSB

DATA

ADDR

17

1

0

ADDR

Target Register

1

R register

0

N register

2.1.1 Register Map

Register Most Significant Bit

SHIFT REGISTER BIT LOCATION

Least Significant Bit

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Data Field

ADDR

R

R_OPT [2:0]

LD_OUT [1:0]

PD_POL

CP_TRI

R_CNTR [9:0]

1

N

NB_CNTR [9:0]

NA_CNTR [4:0]

PD [1:0]

0

2.2 R REGISTER

The R register contains the R_CNTR, CP_TRI, PD_POL, LD_OUT, R_OPT control words. The detailed descriptions and

programming information for each control word is discussed in the following sections.

Register

Most Significant Bit

SHIFT REGISTER BIT LOCATION

Least Significant Bit

17

16

15

14

13

12

11

10

9876

543210

Data Field

ADDR

R

R_OPT [2:0]

LD_OUT [1:0]

PD_POL

CP_TRI

R_CNTR [9:0]

1

www.national.com

22